3-dimensional stack memory device

Patent metadata

Field	Value
Publication number	US-9659999-B2
Application number	US-201514960203-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Aug 23, 2012
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.

First claim

What is claimed is:

1. A stack memory device, comprising:
a semiconductor substrate;
a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate;
a gate electrode formed in the stacked active pattern;
a source and drain formed at both sides of the gate electrode in each of the plurality of active regions;
a bit line formed on one side of the drain to be connected to the drain;
a resistive device layer formed on one side of the source to be connected to the source; and
a source line connected to the resistive device layer,
wherein the source is configured of an impurity region having a first conductive type, and the drain is configured of an impurity region having a second conductive type different from the first conductivity type,
wherein each of the plurality of active regions includes the first conductive type impurities or the second conductive type impurities and the active region includes a low impurity-concentration relative to that of the source or drain, and
wherein the gate electrode is disposed to be biased to the source or the drain.

2. The stack memory device of claim 1 , further comprising a word line disposed over the stacked active pattern, connected to the gate electrode, and extending in a first direction.

3. The stack memory device of claim 2 , wherein the plurality of stacked active patterns and the plurality of word lines are provided, and
the stacked active pattern and the word line are disposed substantially parallel to each other.

4. The stack memory device of claim 3 , wherein the bit line is configured to extend in a second direction substantially perpendicular to the first direction and is commonly connected to the drains of the plurality of active regions disposed on the same plane.

5. The stack memory device of claim 4 , wherein the source line is configured to be commonly connected to the resistive device layers of the stacked active pattern, which is disposed substantially parallel in the second direction.

6. The stack memory device of claim 4 , wherein the source line is configured to be connected to the resistive device layers of the stacked active pattern.

7. The stack memory device of claim 1 , wherein the resistive device layer includes a PrCaMnO (PCMO) layer, a chalcogenide layer, a magnetic layer, a magnetization reversal device layer, or a polymer layer.

8. A stack memory device, comprising:
a plurality of switching devices disposed in a stack structure on a semiconductor substrate, each switching device including a source, a drain and a gate electrode formed between the source and the drain;
a plurality of bit lines each connected to a first electrode of each of the switching devices disposed in the stack structure;
resistive device layers each connected to a second electrode of each of the switching devices disposed in the stack structure; and
a source line commonly connected to the resistive device layers,
wherein the switching devices include a tunnel field effect transistor (FET) and the gate electrode is disposed to be biased to the drain or source, and
wherein the drain and the source have different conductive types from each other.

9. The stack memory device of claim 8 , wherein
each gate electrode is formed on a portion of a plurality of active regions;
each drain is formed at a first side of the gate electrode in the plurality of active regions, as the first electrode; and
each source is formed at a second side of the gate electrode in the plurality of active regions, as the second electrode.

10. The stack memory device of claim 9 , wherein the gate electrode is configured to be disposed on a top of an uppermost active region of the plurality of active regions and sides of the plurality of active regions.

11. The stack memory device of claim 8 , wherein each of the plurality of active regions between the source and drain is an intrinsic semiconductor layer.

12. The stack memory device of claim 8 , wherein each of the plurality of active regions between the source and drain is an impurity region having substantially the same conductive type as the drain or the source.

Assignees

• Sk Hynix Inc

Inventors

• Park Nam Kyun

Classifications

• H01L45/14

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10B63/845 Primary

  the switching components being connected to a common vertical conductor · CPC title