Printed circuit board including a thick-wall via and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-2017367185-A1
Application number	US-201615188681-A
Country	US
Kind code	A1
Filing date	Jun 21, 2016
Priority date	Jun 21, 2016
Publication date	Dec 21, 2017
Grant date	—

Abstract

A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.

First claim

What is claimed is:

1 . A method of manufacturing a printed circuit board, said method comprising:
providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer; forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, the first via hole defined by a first sidewall of the PCB substrate; forming a second via hole in the PCB substrate, the second via hole defined by a second sidewall of the PCB substrate; and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, wherein the first via and the second via have different via sidewall thicknesses.

2 . A method in accordance with claim 1 , wherein selectively plating the first sidewall and the second sidewall comprises selectively plating the first sidewall and the second sidewall such that at least one of the first via and the second via has a via sidewall with an average radial thickness of at least 2.5 mils (0.0025 inches), and a conductive pad with an average thickness of no more than 3.2 mils (0.0032 inches).

3 . A method in accordance with claim 1 , wherein selectively plating the first sidewall and the second sidewall comprises:
performing a first plating process on the PCB substrate, prior to the second via hole being formed, to deposit a first plating layer on the first sidewall; and performing a second plating process on the PCB substrate, subsequent to the second via hole being formed, to deposit a second plating layer on the first plating layer and a third plating layer on the second sidewall.

4 . A method in accordance with claim 3 , further comprising determining a radial thickness of the first plating layer to be deposited during the first plating process based on an estimated plating time of at least one other plating process performed subsequent to the first plating process.

5 . A method in accordance with claim 3 , wherein performing the first plating process and performing the second plating process comprises depositing the first plating layer and depositing the second plating layer such that a combined radial thickness of the first and second plating layers is at least 2.5 mils (0.0025 inches).

6 . A method in accordance with claim 3 , further comprising:
forming a third via hole in the PCB substrate subsequent to the second plating process, the third via hole defined by a third sidewall of the PCB substrate; and performing a third plating process on the PCB substrate to deposit a fourth plating layer on the second plating layer, a fifth plating layer on the third plating layer, and a sixth plating layer on the third sidewall.

7 . A method in accordance with claim 3 , wherein at least one of the first plating process and the second plating process comprises a pulse plating process.

8 . A method in accordance with claim 3 , wherein providing a printed circuit board (PCB) substrate includes providing a PCB substrate wherein at least one of the first conductive layer and the second conductive layer is covered by a mask, and wherein the method further comprises:
removing the mask subsequent to the first plating process; and wherein performing the second plating process further includes forming an outer plating layer on at least one of the first conductive layer and the second conductive layer.

9 . A method in accordance with claim 1 , wherein forming a second via hole includes forming the second via hole such that the second via hole extends from at least one of the first conductive layer and the second conductive layer.

10 . A method in accordance with claim 1 , wherein forming the first via hole includes mechanically drilling the first via hole in the PCB substrate, and wherein forming the second via hole includes mechanically drilling the second via hole in the PCB substrate.

11 . A method in accordance with claim 1 , wherein forming the second via hole in the PCB substrate includes forming the second via hole such that the second via hole has a smaller diameter than the first via hole.

12 . A method in accordance with claim 1 , further comprising electrically coupling an electronic component to at least one of the first via and the second via.

13 . A method in accordance with claim 12 , wherein electrically coupling an electronic component comprises electrically coupling at least one of a transformer, an inductor, and a power MOSFET to at least one of the first via and the second via.

14 . A printed circuit board comprising:
at least one insulating layer; first and second conductive layers separated from one another by said at least one insulating layer; and a conductive via extending through said at least one insulating layer and electrically coupling said first and second conductive layers, said conductive via including an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches), and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).

15 . A printed circuit board in accordance with claim 14 , wherein the average radial thickness of said sidewall is at least about 3 mils (0.003 inches).

16 . A printed circuit board in accordance with claim 14 , wherein the average thickness of said conductive pad is no more than about 2.5 mils (0.0025 inches).

17 . A printed circuit board in accordance with claim 14 , wherein at least one of said first conductive layer and said second conductive layer is an outermost conductive layer of said printed circuit board, said outermost conductive layer comprising a plurality of conductive traces, said conductive pad disposed within said outermost conductive layer.

18 . A printed circuit board in accordance with claim 17 , wherein said plurality of conductive traces includes at least one pair of conductive traces having a center-to-center spacing of no more than 25 mils (0.025 inches).

19 . A printed circuit board in accordance with claim 14 , wherein said via sidewall is a substantially straight, vertical sidewall extending from said first conductive layer to said second conductive layer.

20 . A printed circuit board assembly comprising:
at least one insulating layer; first and second conductive layers separated from one another by said at least one insulating layer; a conductive via extending through said at least one insulating layer and electrically coupling said first and second conductive layers, said conductive via including an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches), and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches); and an electronic component electrically coupled to said conductive via, said electronic component comprising a pair of conductive leads having a center-to-center spacing of less than about 0.025 inches.

Assignees

• Gen Electric

Inventors

• Roessler Robert Joseph

Classifications

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K3/429 Primary

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K3/303

  with surface mounted components (H05K3/32 takes precedence) · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title