Methods of forming substrate microvias with anchor structures

Patent metadata

Field	Value
Publication number	US-9245795-B2
Application number	US-201313903368-A
Country	US
Kind code	B2
Filing date	May 28, 2013
Priority date	May 28, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region.

First claim

What is claimed is:

1. A structure comprising:
a first conductive layer disposed in an opening of a package substrate, wherein a portion of the first conductive layer is disposed in and entirely covering a bottom of an anchor region, wherein the anchor region is disposed underneath a bottom portion of a dielectric layer, wherein the dielectric layer is adjacent the opening;
another portion of the first conductive layer disposed in the opening abutting the dielectric layer, wherein the portion of the first conductive layer disposed in the anchor region does not contact the another portion of the first conductive layer disposed in the opening; and
a second conductive layer disposed on the first conductive layer.

2. The structure of claim 1 wherein the first conductive layer comprises titanium and the second conductive layer comprises copper.

3. The structure of claim 1 further comprising wherein the first conductive layer comprises a PVD titanium material, and wherein the second conductive layer comprises a PVD copper seed material.

4. The structure of claim 1 further comprising wherein the opening comprises a microvia opening, wherein the microvia opening comprises an undercut region, and wherein the undercut region comprises a bottom region and an adjacent anchor region.

5. The structure of claim 1 wherein the package substrate comprises a portion of a 3d multi-chip package substrate.

6. The structure of claim 1 wherein an electrolytic copper material is disposed on the second conductive layer.

7. The structure of claim 1 further comprising wherein a first portion of the second conductive layer is disposed in the anchor region, and wherein a second portion of the second conductive layer is disposed in a bottom portion of the opening.

8. The structure of claim 1 wherein the package substrate is coupled with a CPU.

9. The structure of claim 1 wherein the package substrate comprises a portion of a system on a chip.

10. The structure of claim 1 further comprising a system comprising:
a bus communicatively coupled to the structure; and
an eDRAM communicatively coupled to the bus.

11. The structure of claim 1 wherein the second conductive layer is disposed on the first conductive layer in the anchor region, and wherein the second conductive layer is substantially continuous between the bottom portion of the opening and the anchor region.

Assignees

• Intel Corp

Inventors

• Boyapati Sri Ranga Sai
• Zhang Qinglei

Classifications

• H10W70/66

  Conductive materials thereof · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title