Semiconductor device with electromagnetic interference film and method of manufacture

Patent metadata

Field	Value
Publication number	US-12243833-B2
Application number	US-202017086712-A
Country	US
Kind code	B2
Filing date	Nov 2, 2020
Priority date	Nov 29, 2016
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

First claim

What is claimed is:

1. A method comprising:
placing a plurality of semiconductor devices on a polymer layer, wherein each of the semiconductor devices comprises a semiconductor substrate and a conductive feature over the semiconductor substrate, wherein each conductive feature has an exposed sidewall that is coplanar with the respective semiconductor substrate;
depositing a continuous conductive film conformally over the polymer layer and over the plurality of semiconductor devices, wherein depositing the conductive film comprises depositing a conductive adhesive layer and depositing a conduction layer on the conductive adhesive layer, wherein the conductive adhesive layer and the conduction layer are electrically conductive, wherein the conductive adhesive layer physically and electrically contacts the exposed sidewall of the conductive feature of each semiconductor device of the plurality of semiconductor devices;
forming an encapsulant on the conductive film, wherein surfaces of the encapsulant, the conductive film, and the conductive features of the plurality of semiconductor devices are coplanar; and
forming a redistribution layer (RDL) covering and physically contacting the plurality of semiconductor devices and the encapsulant, wherein the RDL is electrically connected to the conductive features of the plurality of semiconductor devices.

2. The method of claim 1 , wherein depositing the conductive film comprises:
depositing the conductive adhesive layer over the plurality of semiconductor devices and between the plurality of semiconductor devices; and
depositing the conduction layer over the conductive adhesive layer.

3. The method of claim 2 , wherein the conductive adhesive layer comprises stainless steel (SUS).

4. The method of claim 2 , wherein the conduction layer comprises copper.

5. The method of claim 1 , further comprising performing a planarization process after forming the encapsulant, the planarization process exposes the conductive features of the plurality of semiconductor devices.

6. The method of claim 1 , wherein the RDL comprises a dielectric layer and a metal layer, wherein a sidewall of the dielectric layer, a sidewall of the metal layer, and a sidewall of the encapsulant are coplanar.

7. The method of claim 1 , wherein a bottom surface of the conductive film and a bottom surface of each semiconductor device of the plurality of semiconductor devices are coplanar.

8. The method of claim 1 , wherein the encapsulant is free of the conductive adhesive layer.

9. A method comprising:
depositing a polymer layer over a carrier;
attaching a first semiconductor device to a top surface of the polymer layer, wherein the first semiconductor device comprises a metal layer over a semiconductor substrate, wherein a sidewall of the metal layer is coplanar with a sidewall of the semiconductor substrate;
depositing a conductive film extending from a top surface of the first semiconductor device to the top surface of the polymer layer, wherein the conductive film physically and electrically contacts the sidewall of the metal layer and physically contacts the sidewall of the semiconductor substrate, wherein the conductive film comprises an inner adhesive layer and an outer conduction layer;
depositing an encapsulant on the conductive film; and
forming a redistribution layer extending over the first semiconductor device and the encapsulant, wherein the redistribution layer is electrically connected to the metal layer.

10. The method of claim 9 further comprising performing a surface treatment process on a sidewall of the encapsulant and a sidewall of the redistribution layer.

11. The method of claim 9 further comprising removing the conductive film from the top surface of the first semiconductor device prior to forming the redistribution layer.

12. The method of claim 9 , wherein the inner adhesive layer comprises stainless steel (SUS) and the outer conduction layer comprises copper.

13. A method of forming a semiconductor package comprising:
depositing an insulating layer over a carrier;
attaching a back side of a first semiconductor device to the insulating layer, wherein the first semiconductor device comprises a conductive via;
depositing an Electromagnetic Interference (EMI) film on the first semiconductor device and on the insulating layer, wherein the EMI film covers sidewalls of the first semiconductor device, wherein the EMI physically and electrically contacts a sidewall of the conductive via;
depositing an encapsulant on the EMI film;
performing a planarization process, wherein after performing the planarizing process, surfaces of the encapsulant, the EMI film, and the conductive via are level; and
forming a redistribution structure over the first semiconductor device, the encapsulant, and the EMI film.

14. The method of claim 13 further comprising:
performing a surface treatment process on sidewalls of the encapsulant and the redistribution structure; and
depositing a conductive layer on the sidewalls of the encapsulant and the redistribution structure, wherein the conductive layer physically and electrically contacts the redistribution structure.

15. The method of claim 14 , wherein the surface treatment process comprises a surface roughening process.

16. The method of claim 13 , wherein sidewalls of the redistribution structure, the insulating layer, the EMI film, and the encapsulant are coplanar.

17. The method of claim 13 further comprising attaching a back side of a second semiconductor device to the insulating layer, wherein the EMI film extends from a sidewall of the first semiconductor device to a sidewall of the second semiconductor device.

18. The method of claim 17 , wherein the second semiconductor device comprises a conductive feature, wherein the EMI film physically and electrically contacts the conductive feature.

19. The method of claim 13 , wherein the redistribution structure physically and electrically contacts the conductive via.

20. The method of claim 13 , wherein depositing the EMI film comprises depositing a layer of stainless steel (SUS) and depositing a layer of copper over the layer of SUS.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chi-Hsi
• Chen Hsien-Wei
• Huang Li-Hsien
• Yang Tien-Chung

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title