Semiconductor package

Patent metadata

Field	Value
Publication number	US-12243791-B2
Application number	US-202217749825-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	Nov 9, 2018
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a metal layer on a carrier;
forming a conductor pattern layer on the metal layer;
mounting a semiconductor chip on a tape;
forming an encapsulant covering the semiconductor chip;
attaching the conductor pattern layer to the encapsulant;
removing the tape; and
forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed,
wherein the metal layer comprises a metal plate having a substantially uniform thickness on the carrier,
the conductor pattern layer comprises a plurality of patterns spaced apart from each other on the metal layer, and
the encapsulant extends between the plurality of patterns and contacts the metal plate.

2. The method of claim 1 , wherein the forming the conductor pattern layer comprises:
forming a first conductor layer with an electroless plating process; and
forming a second conductor layer on the first conductor layer with an electrolytic plating process.

3. The method of claim 2 , wherein a thickness of the first conductor layer is smaller than a thickness of the second conductor layer.

4. The method of claim 2 , wherein at least one of the first conductor layer and the second conductor layer is formed by a plating process of one of an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), and a tenting process.

5. The method of claim 1 , wherein the connection structure includes one or more redistribution layers, and
a thickness of each of the one or more redistribution layers is thinner than a thickness of the conductor pattern layer.

6. The method of claim 1 , further comprising:
forming a frame including a through-hole on the tape before the mounting the semiconductor chip,
wherein the semiconductor chip is mounted in the through-hole, and
wherein the frame includes a first insulation layer in contact with the connection structure, a first wiring layer in contact with the connection structure and embedded in the first insulation layer, a second wiring layer disposed on a side of the first insulation layer opposite to a side on which the first wiring layer is disposed, a second insulation layer disposed on the first insulation layer and covering the second wiring layer, and a third wiring layer disposed on a side of the second insulation layer opposite to a side in which the second wiring layer is embedded, and
the first to third wiring layers are electrically connected to the semiconductor chip.

7. The method of claim 1 , further comprising:
forming a frame including a through-hole on the tape before the mounting the semiconductor chip,
wherein the semiconductor chip is mounted in the through-hole, and
wherein the frame includes an insulation layer in which the through-hole is formed, first and second metal layers respectively disposed on opposing surfaces of the insulation layer, and a third metal layer disposed on a wall surface of the through-hole.

8. The method of claim 1 , further comprising:
removing the carrier;
forming a conductive adhesive in an area from which the carrier is removed; and
forming a heat dissipating member on the conductive adhesive.

9. The method of claim 8 , wherein the conductive adhesive comprises a thermally conductive interface material (TIM), and
the heat dissipating member comprises a metal lump.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a conductor pattern layer on a carrier;
forming an upper encapsulant covering the conductor pattern layer on the carrier;
mounting a semiconductor chip on a tape;
forming a lower encapsulant covering the semiconductor chip on the tape;
laminating the lower encapsulant and the upper encapsulant; and
removing the carrier and forming a conductive adhesive and a heat dissipating member sequentially on an area from which the carrier is removed after the laminating the lower encapsulant and the upper encapsulant.

11. The method of claim 10 , wherein the forming of the upper encapsulant comprises forming a first material layer covering the conductor pattern layer and a first curing process of curing the first material layer, and
the forming of the lower encapsulant comprises forming a second material layer covering the semiconductor chip, and a second curing process of curing the second material layer.

12. The method of claim 11 , wherein the first curing process and the second curing process are respectively performed before the laminating the lower encapsulant and the upper encapsulant.

13. The method of claim 11 , wherein the first curing process and the second curing process are performed simultaneously in a step of the laminating the lower encapsulant and the upper encapsulant.

14. The method of claim 10 , further comprising:
removing the tape after the laminating the lower encapsulant and the upper encapsulant; and
forming a connection structure in an area from which the tape is removed,
wherein the connection structure is electrically connected to the semiconductor chip.

15. The method of claim 10 , further comprising:
forming a metal layer on the carrier before the forming the conductor pattern layer.

16. The method of claim 15 , wherein the conductive adhesive is in contact with the metal layer, and is spaced apart from the conductor pattern layer by the metal layer.

17. A method of manufacturing a semiconductor device, the method comprising:
forming a metal layer on a carrier;
forming a conductor pattern layer on the metal layer;
forming an upper encapsulant covering the conductor pattern layer on the metal layer;
mounting a semiconductor chip on a tape;
forming a lower encapsulant covering the semiconductor chip on the tape; and
laminating the lower encapsulant and the upper encapsulant,
wherein the metal layer is in a form of a metal plate, and
the conductor pattern layer includes a plurality of patterns spaced apart from each other on the metal plate.

18. The method of claim 17 , further comprising:
removing the tape and forming a connection structure electrically connected to the semiconductor chip; and
removing the carrier and forming a heat dissipating member on an area from which the carrier is removed,
wherein the upper encapsulant extends between the plurality of patterns and contacts the metal layer.

19. The method of claim 18 , wherein the plurality of patterns are disposed to be spaced apart from the semiconductor chip by a predetermined distance.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Sunghawn
• Lee Doohwan
• Choi Jooyoung

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title