Method of testing semiconductor package

Patent metadata

Field	Value
Publication number	US-12243788-B2
Application number	US-202318359887-A
Country	US
Kind code	B2
Filing date	Jul 27, 2023
Priority date	Jul 16, 2021
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

A method of testing a semiconductor package includes: forming a charge measurement unit over a carrier substrate; forming a first dielectric layer over the charge measurement unit; forming a first metallization layer over the dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit; performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

First claim

What is claimed is:

1. A method of testing a semiconductor package, comprising:
attaching a charge measurement unit to a carrier substrate via an adhesive layer;
forming a first dielectric layer over the charge measurement unit;
forming a first metallization layer over the first dielectric layer, wherein the forming of the first metallization layer induces first charges to accumulate on the charge measurement unit;
performing a first test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and
in response to determining that no breakdown occurs in the charge measurement unit, forming a second dielectric layer over the first metallization layer.

2. The method of claim 1 , further comprising:
performing a second test against the charge measurement unit to determine whether breakdown occurs in the charge measurement unit; and
in response to determining that no breakdown occurs in the charge measurement unit, forming a second metallization layer over the second dielectric layer.

3. The method of claim 2 , wherein the first metallization layer includes a first conductive pad electrically connected to the charge measurement unit, and the second metallization layer includes a second conductive pad vertically offset from the first conductive pad.

4. The method of claim 3 , further comprising:
forming a plurality of conductive bumps over the second dielectric layer and the second metallization layer, wherein the plurality of conductive bumps are electrically connected to the second metallization layer; and
performing a third test against the charge measurement unit through the plurality of conductive bumps to determine whether breakdown occurs in the charge measurement unit.

5. The method of claim 3 , wherein the first metallization layer further includes a third conductive pad electrically connected to the charge measurement unit.

6. The method of claim 5 , wherein the first conductive pad is configured to contact two first test probes and the third conductive pad is configured to contact two second test probes during the first test, and the first conductive pad and the third conductive pad are respectively configured as input and output terminals during the first test.

7. The method of claim 5 , wherein the first conductive pad is configured to contact a first test probe and the third conductive pad is configured to contact a second test probe during the first test, and the first conductive pad and the third conductive pad are both configured as input terminals during the first test.

8. The method of claim 5 , wherein the performing of the first test further comprises determining whether a signal is transmitted between the first conductive pad and the third conductive pad.

9. The method of claim 1 , further comprising forming a charge receiving unit over the carrier substrate adjacent to the charge measurement unit, the charge receiving unit comprising a semiconductor substrate.

10. The method of claim 9 , wherein the charge receiving unit further comprises a conductive mesh disposed over the semiconductor substrate.

11. A method of testing a semiconductor package, comprising:
providing a carrier substrate;
attaching a first charge measurement unit and a second charge measurement unit to the carrier substrate via an adhesive layer;
forming a first metallization layer over the first charge measurement unit and the second charge measurement unit;
performing a first test against the first charge measurement unit to determine whether breakdown occurs in the first charge measurement unit;
performing a second test against the second charge measurement unit to determine whether breakdown occurs in the second charge measurement unit in response to determining that breakdown occurs in the first charge measurement unit; and
in response to determining that no breakdown occurs in the second charge measurement unit, forming a first dielectric layer over the first metallization layer.

12. The method of claim 11 , further comprising forming a first conductive pad and a second conductive pad in the first metallization layer, wherein the first conductive pad and the second conductive pad are exposed through the first dielectric layer.

13. The method of claim 11 , wherein a first breakdown voltage of the first charge measurement unit is different from a second breakdown voltage of the second charge measurement unit.

14. The method of claim 11 , further comprising determining a specification of an electrostatic discharge protection circuit according to a test result of the first test and the second test.

15. The method of claim 11 , wherein the first charge measurement unit includes a first capacitor, the first capacitor includes a first electrode, a second electrode and a second dielectric layer between the first electrode and the second electrode.

16. The method of claim 15 , wherein the second charge measurement unit includes two second capacitors connected in series, and each of the second capacitor includes a third electrode, a fourth electrode and a third dielectric layer between the third electrode and the fourth electrode, wherein a breakdown voltage of the second dielectric layer is identical to a breakdown voltage of the third dielectric layer.

17. A method of testing a semiconductor package, comprising:
providing a carrier substrate having a first charge measurement unit and a second charge measurement unit attached thereto via an adhesive layer;
forming a first metallization layer over the carrier substrate by a first charge-induced operation;
performing a first test against the first charge measurement unit to determine whether breakdown occurs in the first charge measurement unit;
in response to determining that no breakdown occurs in the first charge measurement unit, forming a second metallization layer over the first metallization layer by a second charge-induced process;
performing a second test against the first charge measurement unit or the second charge measurement unit to determine whether breakdown occurs in the first charge measurement unit or the second charge measurement unit; and
in response to determining that no breakdown occurs in the first and second charge measurement units, forming a third metallization layer over the second metallization layer.

18. The method of claim 17 , further comprising:
performing a third test against the first charge measurement unit or the second charge measurement unit to determine whether breakdown occurs in the first charge measurement unit or the second charge measurement unit.

19. The method of claim 17 , wherein a breakdown occur in the first charge measurement unit prior to the second charge measurement unit.

20. The method of claim 17 , wherein the first charge measurement unit and the second charge measurement unit respectively include a conductive mesh.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chi-Hui
• Chen Yang-Che
• Lin Chen-Hua
• Liang Victor Chiang
• Liu Chwen-Ming

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title