Electronic device having multilayered substrate and manufacturing method thereof

US12232260B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12232260-B2
Application numberUS-202217939546-A
CountryUS
Kind codeB2
Filing dateSep 7, 2022
Priority dateMar 18, 2022
Publication dateFeb 18, 2025
Grant dateFeb 18, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other, a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened. 2. The electronic device of claim 1 , wherein a length of the conductive line between the first conductive via and the connector are substantially equivalent to a length of the conductive line between the second conductive via and the connector. 3. The electronic device of claim 1 , wherein the conductive line is divided into divided conductive lines by the connector, and the divided conductive lines have substantially equivalent impedances as each other. 4. The electronic device of claim 3 , wherein the divided conductive lines have different lengths from each other, and the divided conductive lines have different widths from each other. 5. The electronic device of claim 1 , wherein an impedance of the open stub relates to an impedance of the conductive line. 6. The electronic device of claim 5 , wherein an impedance of the open stub is ½ of the impedance of the conductive line. 7. The electronic device of claim 1 , wherein the open stub is disposed on a same layer as the conductive line. 8. The electronic device of claim 1 , wherein the open stub is a conductive via penetrating the plurality of substrate bases. 9. The electronic device of claim 1 , wherein the open stub extends to cross the conductive line. 10. The electronic device of claim 1 , wherein the open stub includes a first open stub and a second open stub, wherein the first open stub extends in a first direction, and the second open stub extends in a second direction different from the first direction. 11. The electronic device of claim 1 , further comprising an additional conductive line disposed on a same layer as the conductive line and disposed adjacent to the conductive line, wherein the open stub extends from the conductive line and is spaced apart from the additional conductive line. 12. The electronic device of claim 1 , wherein the open stub is a plurality of open stubs, wherein the plurality of open stubs are connected to the conductive line at connectors in the conductive line, wherein the conductive line is divided into a plurality of divided conductive lines by the connectors, wherein lengths of at least two of divided conductive lines of the plurality of divided conductive lines are substantially equivalent to each other. 13. The electronic device of claim 1 , wherein the open stub is a plurality of open stubs, and impedances of at least two open stubs of the plurality of open stubs are substantially equivalent to each other. 14. The electronic device of claim 1 , further comprising: a first semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the first conductive via; and a second semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the second conductive via. 15. The electronic device of claim 1 , further comprising: a first semiconductor chip attached to one side of the multilayered base substrate and electrically connected to the first conductive via; and an input/output terminal disposed on one side of the multilayered base substrate and electrically connected to the second conductive via. 16. An electronic device comprising: a base substrate including a plurality of substrate bases stacked on each other; at least one semiconductor chip attached to a first side of the base substrate; and a conductive pattern connected to the at least one semiconductor chip and having a low pass filter, wherein the low pass filter includes a first conductive via and a second conductive via penetrating the plurality of substrate bases, a conductive line disposed between adjacent substrate bases, of the plurality of substrate bases, that are stacked on each other, wherein the conductive line electrically connects the first conductive via and the second conductive via to each other, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via, and at least one open stub including a first end and a second end, wherein the first end is connected to the conductive line at a connector at which the conductive line is divided into substantially equivalent lengths, wherein the second end is opened. 17. The electronic device of claim 16 , wherein the first conductive via includes a first via stub between a substrate base, of the plurality of substrate bases, on which the conductive line is disposed and a first side of the base substrate, and the second conductive via includes a second via stub between the substrate base on which the conductive line is disposed and a second side of the base substrate. 18. The electronic device of claim 16 , wherein the conductive line, the at least one open stub, and the first and second via stubs form the low pass filter. 19. A method for manufacturing an electronic device, comprising: providing a base substrate including a plurality of substrate bases, wherein a conductive line is formed on a substrate base of the plurality of substrate bases; and forming conductive vias penetrating the base substrate and connected to respective ends of the conductive line, wherein the conductive line is disposed between an upper surface and a lower surface of the first conductive via, wherein the conductive line is connected to an open stub of which a first end is opened in substantially a middle of the conductive line. 20. The method of claim 19 , further comprising: before providing the base substrate, forming the conductive line and the open stub on at least one side of the substrate base.

Assignees

Inventors

Classifications

  • H05K1/0298Primary

    Multilayer circuits · CPC title

  • Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence) · CPC title

  • Special connections between adjacent vias, not for grounding vias · CPC title

  • H05K1/0251Primary

    related to vias or transitions between vias and transmission lines · CPC title

  • Printed circuits associated with mounted high frequency components · CPC title

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What does patent US12232260B2 cover?
An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate base…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/0298. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 18 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).