Apparatus and method for frequency multiplication

Patent metadata

Field	Value
Publication number	US-11855650-B2
Application number	US-202117323437-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	May 19, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal.

First claim

What is claimed is:

1. A frequency multiplication apparatus, the apparatus comprising:
a first frequency multiplier configured to receive a first signal having a first frequency and to output at a node a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer);
a second frequency multiplier configured to receive the second signal at the node and to output a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer); and
a first coupler including a first resistor having an end electrically connected to the node and another end connected to an output port of the frequency multiplication apparatus to output a part of the second signal to an external load.

2. The apparatus of claim 1 , wherein the first frequency multiplier and the second frequency multiplier are connected to each other in series, and
the one end of the first resistor is not electrically connected to the another end of the first resistor.

3. The apparatus of claim 1 , wherein
the first coupler further comprises a second resistor having an end electrically connected to ground and another end electrically connected to the another end of the first resistor.

4. The apparatus of claim 1 , wherein the second frequency and the third frequency are included in a millimeter-wave band or a sub-terahertz-wave band.

5. The apparatus of claim 1 , wherein the second signal of the second frequency and the third signal of the third frequency are provided as signal sources for at least one of 5G mobile communication (5G), 6G mobile communication (6G), wireless personal area network (WPAN), and industrial scientific medical (ISM) communication systems.

6. The apparatus of claim 1 , further comprising:
a third frequency multiplier configured to receive the third signal and to output a fourth signal having a fourth frequency by multiplying the third frequency by ‘k’ (‘k’ being a positive integer),
wherein the third frequency multiplier is connected to an output of the second frequency multiplier in series.

7. The apparatus of claim 6 , further comprising:
a second coupler connected between the output of the second frequency multiplier and an input of the third frequency multiplier and configured to output a part of the third signal.

8. The apparatus of claim 7 , wherein the first frequency multiplier is deactivated, and
wherein the second frequency multiplier receives a fifth signal having a fifth frequency through the first coupler and outputs a sixth signal having a sixth frequency by multiplying the fifth frequency by the ‘m’, and
wherein the third frequency multiplier receives the sixth signal and outputs a seventh signal having a seventh frequency by multiplying the sixth frequency by the ‘k’.

9. The apparatus of claim 7 , wherein the first frequency multiplier and the second frequency multiplier are deactivated,
wherein the third frequency multiplier receives a fifth signal having a fifth frequency through the second coupler and outputs a sixth signal having a sixth frequency by multiplying the fifth frequency by the ‘k’.

10. The apparatus of claim 1 , wherein ‘m’ is not equal to ‘n’.

11. The apparatus of claim 1 , the frequency multiplication apparatus being implemented as a single multiple-input and multiple-output (MIMO) integrated circuit (IC) chip.

12. The apparatus of claim 1 , wherein the first frequency multiplier and the second frequency multiplier are selectively activated and deactivated.

13. A frequency multiplication apparatus, the apparatus comprising:
a first frequency multiplier configured to receive a first signal having a first frequency and to output a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer);
a second frequency multiplier configured to receive the second signal and to output a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer); and
a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and configured to output a part of the second signal, wherein the first frequency multiplier is deactivated, and
wherein the second frequency multiplier receives a fourth signal having a fourth frequency through the coupler and outputs a fifth signal having a fifth frequency by multiplying the fourth frequency by the ‘m’.

14. The apparatus of claim 13 , wherein the fourth frequency is identical to the second frequency.

15. A frequency multiplication method, the method comprising:
in a first operating mode, receiving an initial signal having an initial frequency;
in the first operating mode, generating a first signal having a first multiplication frequency by multiplying the initial frequency by ‘n’ (‘n’ being a positive integer);
in the first operating mode, outputting the first signal to a first external device through a first coupler circuit;
in the first operating mode, generating a second signal having a second multiplication frequency by multiplying the first multiplication frequency by ‘m’ (‘m’ being a positive integer);
in a second operating mode, receiving a first input signal having a first input frequency through the first coupler circuit; and
in the second operating mode, generating a third signal having a third multiplication frequency by multiplying the first input frequency by the ‘m’.

16. The method of claim 15 , wherein the first input frequency is identical to the first multiplication frequency.

17. A frequency multiplication method, the method comprising:
in a first operating mode, receiving an initial signal having an initial frequency;
in the first operating mode, generating a first signal having, a first multiplication frequency by a first frequency multiplier by multiplying the initial frequency by ‘n’ (‘n’ being a positive integer);
in the first operating mode, outputting the first signal to a first external device through a first coupler circuit; and
in the first operating mode, generating a second signal having a second multiplication frequency by a second frequency multiplier by multiplying the first multiplication frequency by ‘m’ (‘m’ being a positive integer), wherein at least one of ‘n’ and ‘m’ is greater than 2,
wherein the first coupler circuit includes two resistors electrically connected in series between an output of the first frequency multiplier and electrical ground, an external load electrically connected in parallel with a one of the two resistors that is connected to electrical ground.

18. A frequency multiplication method, the method comprising:
in a first operating mode, receiving an initial signal having an initial frequency;
in the first operating mode, generating a first signal having a first multiplication frequency by a first frequency multiplier by multiplying the initial frequency by ‘n’ (‘n’ being a positive integer);
in the first operating mode, outputting the first signal to a first external device through a first coupler circuit;
in the first operating mode, generating a second signal having a second multiplication frequency by a second frequency multiplier by multiplying the first multiplication frequency by ‘m’ (‘m’ being a positive integer), wherein at least one of ‘n’ and ‘m’ is greater than 2; and
selectively activating and deactivating the first frequency multiplier and the second frequency multiplier based on whether in the first operating mode or in a second operating mode.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kang Dongwoo

Classifications

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03B19/10 Primary

  using multiplication only · CPC title

• H03B19/14

  by means of a semiconductor device · CPC title

• H03B21/04

  using several similar stages · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title