Implementing backdrilling elimination utilizing via plug during electroplating

US9872398B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9872398-B1
Application numberUS-201615231515-A
CountryUS
Kind codeB1
Filing dateAug 8, 2016
Priority dateAug 8, 2016
Publication dateJan 16, 2018
Grant dateJan 16, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for implementing enhanced via creation without creating a via barrel stub during printed circuit board (PCB) manufacturing comprising: providing a printed circuit board (PCB); said printed circuit board (PCB) having an internal conductive trace; forming a via extending through the printed circuit board (PCB) including the internal conductive trace; inserting a via plug into the via, said via plug having a capillary extending through said via plug; and performing PCB plating. 2. The method as recited in claim 1 includes said via plug remaining in the PCB via after PCB plating. 3. The method as recited in claim 1 includes providing enhanced signal integrity with said via plug. 4. The method as recited in claim 1 includes providing enhanced noise reduction with said via plug. 5. The method as recited in claim 1 includes forming with said via plug with a selected electrically insulating material. 6. The method as recited in claim 1 wherein inserting a via plug into the via includes slidingly inserting said via plug into the via. 7. The method as recited in claim 1 includes forming with said via plug with a specialized geometry and capillary conforming to the via. 8. The method as recited in claim 1 wherein providing a printed circuit board (PCB); said printed circuit board (PCB) having an internal conductive trace includes a standard PCB manufacturing process. 9. The method as recited in claim 1 wherein inserting said via plug into the via includes providing an arrayed tool used to insert multiple ones of said via plugs at once. 10. The method as recited in claim 1 includes performing a standard PCB plating process responsive to inserting the via plug. 11. The method as recited in claim 1 includes performing conventional PCB finishing processes with aid via plug remaining in the PCB via after PCB plating. 12. The method as recited in claim 1 wherein eliminating via back-drilling enables improved yield and reliability of the PCB.

Assignees

Inventors

Classifications

  • Printed elements for providing electric connections to or between printed circuits · CPC title

  • Drilling of holes · CPC title

  • H05K3/42Primary

    Plated through-holes {or plated via connections} · CPC title

  • Conductive traces · CPC title

  • Plated through-holes or blind vias without lands · CPC title

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Frequently asked questions

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What does patent US9872398B1 cover?
A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H05K3/42. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).