Modification of electric fields of compound semiconductor devices

Patent metadata

Field	Value
Publication number	US-12230699-B2
Application number	US-202017067988-A
Country	US
Kind code	B2
Filing date	Oct 12, 2020
Priority date	Oct 23, 2019
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.

First claim

What is claimed is:

1. An integrated circuit including a back-side field plate to modify an electric field produced by at least one semiconductor device, the integrated circuit comprising:
a substrate including a plurality of conductive layers disposed in a region of the substrate, the plurality of conductive layers comprising at least a portion of the back-side field plate and including a first conductive layer comprising a p-type material, a second conductive layer comprising the p-type material, and an additional layer including an n-type material disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer is located at a first depth in the substrate and the second conductive layer is located at a second depth in the substrate, the second depth being different from the first depth, and wherein the first conductive layer modifies a first range of electric field strengths and the second conductive layer modifies a second range of electric field strengths that is different from the first range of electric field strengths;
a channel layer disposed on a surface of the substrate, the channel layer being comprised of a first compound material having a Group 13 element and Group 15 element; and
a barrier layer disposed on the channel layer, the barrier layer being comprised of a second compound material having a Group 13 element and a Group 15 element.

2. The integrated circuit of claim 1 , wherein:
the barrier layer includes aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (AlInGaN);
the substrate is comprised of at least one of Si, SiC, sapphire, aluminum nitride (AlN), or polycrystalline AlN; and
the channel layer includes GaN, gallium arsenide (GaAs), indium phosphide (InP), or AlN.

3. The integrated circuit of claim 1 , wherein the region that includes the plurality of conductive layers is adjacent to a surface of the substrate or forms a surface of the substrate.

4. The integrated circuit of claim 1 , comprising:
a first dielectric layer disposed on the barrier layer; and
a second dielectric layer disposed on the first dielectric layer;
wherein a source electrical contact and a drain electrical contact extend through the first dielectric layer and the second dielectric layer.

5. The integrated circuit of claim 4 , wherein a gate electrical contact, the source electrical contact, and the drain electrical contact are part of a high electron mobility transistor (HEMT).

6. The integrated circuit of claim 5 , comprising a field plate disposed over at least a portion of the gate electrical contact and the plurality of conductive layers are aligned with at least a portion of the gate electrical contact and at least a portion of the field plate.

7. The integrated circuit of claim 5 , wherein the back-side field plate disposed over at least the portion of the gate electrical contact includes a first additional conductive layer vertically aligned with the first conductive layer and a second additional conductive layer vertically aligned with the second conductive layer.

8. The integrated circuit of claim 1 , wherein:
the substrate includes a p-type material.

9. The integrated circuit of claim 1 , wherein the first conductive layer is offset laterally with respect to the second conductive layer.

10. The integrated circuit of claim 1 , wherein a thickness of the channel layer and a nucleation layer disposed adjacent to the channel layer is from about 50 nm to about 500nm.

11. A semiconductor device including a back-side field plate to modify an electric field produced by the semiconductor device, the semiconductor device comprising:
a semiconductor device substrate including a plurality of conductive layers disposed in the semiconductor device substrate, a first conductive layer of the plurality of conductive layers being located at a first depth in the semiconductor device substrate and including an n-type material and a second conductive layer of the plurality of conductive layers being located at a second depth in the semiconductor device substrate and including the n-type material, the second depth being different from the first depth, and wherein the first conductive layer modifies a first range of electric field strengths, the second conductive layer modifies a second range of electric field strengths that is different from the first range of electric field strengths, and an additional layer including a p-type material is disposed between the first conductive layer and the second conductive layer; and
a compound semiconductor layer disposed on the semiconductor device substrate and the compound semiconductor layer including a channel layer and a barrier layer, the channel layer being comprised of a compound material having a Group 13 element and Group 15 element.

12. The semiconductor device of claim 11 , wherein the first conductive layer is offset laterally from the second conductive layer.

13. The semiconductor device of claim 11 , wherein the first conductive layer and the second conductive layer are coupled to a drain electrical contact.

14. The semiconductor device of claim 11 , wherein the first range of electric field strengths is from about 1 Volt/meter (V/m) to about 20 V/m and the second range of electric field strengths is from about 20 V/m to about 40 V/m.

15. The semiconductor device of claim 11 , wherein the first depth is from about 10nm to about 500 nm and the second depth is from about 400 nm to about 2000 nm.

16. A process to modify an electric field produced by a semiconductor device comprises:
forming a first conductive layer located at a first depth of a substrate and a second conductive layer at a second depth of the substrate, wherein the second depth is different from the first depth, the first conductive layer includes a p-type material, the second conductive layer includes the p-type material, and an additional layer including an n-type material is disposed between the first conductive layer and the second conductive layer;
disposing a compound semiconductor layer on the substrate, the compound semiconductor layer including a barrier layer and a channel layer, the channel layer being comprised of a compound material having a Group 13 element and Group 15 element; and
forming the semiconductor device with the compound semiconductor layer;
wherein the first conductive layer is configured to modify a first range of electric field strengths and the second conductive layer is configured to modify a second range of electric field strengths that is different from the first range of electric field strengths.

17. The process of claim 16 , wherein forming the first conductive layer and the second conductive layer in the substrate comprises performing one or more implantation processes to dispose a conductive material within the substrate.

18. The process of claim 17 , comprising:
forming a first dielectric layer on the substrate;
forming a second dielectric layer on the first dielectric layer; and
forming a pattern in the second dielectric layer.

19. The process of claim 18 , wherein:
the one or more implantation processes produce one or more portions of at least one of the first conductive layer or the second conductive layer within the substrate according to the pattern; and
the process comprises removing the first dielectric layer and the second dielectric layer before disposing the compound semiconductor layer on the substrate.

20. The process of claim 16 , wherein:
the substrate is free of divots before dispo

Assignees

• Analog Devices Inc

Inventors

• Piedra Daniel
• Fiorenza James G
• Srivastava Puneet

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title