GaN semiconductor device structure and method of fabrication by substrate replacement

Patent metadata

Field	Value
Publication number	US-9818692-B2
Application number	US-201615078023-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Dec 12, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

First claim

The invention claimed is:

1. A nitride semiconductor device comprising:
a GaN die comprising a lateral GaN transistor, the GaN die being sandwiched between an overlying header and an underlying composite thermal dielectric layer;
the GaN die comprising:
a GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for the lateral GaN transistor, and at least one underlying layer;
one or more layers of on-chip metallization being provided on a front side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, the on-chip metallization defining source and drain electrodes of the lateral GaN transistor, a gate electrode formed on a channel region between the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes; and
the overlying header comprising:
a support substrate comprising a dielectric material having a coefficient of thermal expansion (CTE) closely matched to the CTE of the GaN epi-layer stack and a conductive metallization layer formed on the support substrate defining conductive tracks for source, drain and gate interconnections;
the overlying header being attached to the GaN die by low inductance conductive interconnections between the contact pads for the source, drain and gate electrodes of the lateral GaN transistor and corresponding source, drain and gate contact areas of the conductive tracks of the overlying header;
a conductive layer in direct contact with a back-side of the GaN-epilayer stack, the conductive layer being patterned to define one or more back-side field plates of the lateral GaN transistor;
the composite thermal dielectric layer comprising:
a high dielectric strength polymer dielectric and a dielectric filler,
the high dielectric strength polymer dielectric comprising one of a polyimide and an epoxy, and the dielectric filler being a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride, Aluminum Nitride , Silicon Nitride, diamond, and mixtures thereof,
the composite thermal dielectric layer forming a coating in direct contact with the back-side of the GaN epi-layer stack and a backside of the one or more back-side field plates, and
wherein the composite thermal dielectric layer has a dielectric strength of at least 40V/μm and a thermal conductivity of about 2W/m.K or more, and the composite thermal dielectric layer has a thickness that provides a breakdown voltage of at least 850V and a thermal resistance of less than 1° C./W.

2. The device of claim 1 , wherein:
when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TPI) and the dielectric filler is selected from the group consisting of a micro-particulate form of Boron Nitride, Aluminum Nitride, Silicon Nitride, and diamond, and
said micro-particulate form comprising micro-particles, micro-flakes, micro-platelets, micro-fibers, nano-particles, nano-platelets, nano-tubes, nano-fibers, and mixtures thereof.

3. The device of claim 1 , wherein:
when the high dielectric strength polymer dielectric comprises a polyimide, the polyimide comprises a thermoplastic polyimide (TPI) and the dielectric filler is selected from the group consisting: Boron Nitride Nano-Tubes (BNNT); Cubic boron nitride powder (c-BN), Boron Nitride nano-particles; hexagonal Boron Nitride flakes (h-BN); and mixtures thereof.

4. The device of claim 1 , wherein said dielectric strength is at least 100 V/μm and said thermal conductivity is in the range from about 2 W/m.K to 5W/m.K, and said thickness of the composite thermal dielectric layer being in the range from 10 μm to 50 μm wherein said breakdown voltage is in the range from 850V to 2000V and said thermal resistance is less than 1° C./W.

5. The device of claim 3 , wherein the dielectric filler of the composite thermal dielectric layer comprises a particle size and filler fraction such that said dielectric strength is at least 100V/μm and said thermal conductivity is in the range from about 2 W/m.K to 5 W/m.K, and wherein when said thickness of the composite thermal dielectric layer is in the range from 10 μm to 50 μm, said breakdown voltage is in the range from 850V to 2000V and said thermal resistance is less than 1° C./W.

6. The device structure of claim 1 , wherein the composite thermal dielectric layer comprises one or more spin-coated layers.

7. The device structure of claim 1 , further comprising a heatspreader layer of a material having a high dielectric strength and a high thermal conductivity selected from the group consisting of Boron Nitride (BN), Aluminum Nitride (AlN), Silicon Nitride (Si 3 N 4 ), and diamond (C), the heatspreader layer being bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.

8. The device structure of claim 1 , further comprising a heatspreader comprising a thermally conductive layer of a ceramic, a metal or a metal alloy, the heatspreader being adhesively bonded to the back-side of the GaN epi-layer stack by said composite thermal dielectric layer.

9. The device structure of claim 1 , wherein the conductive layer defining the one or more back-side field plates comprises a metal filled thermoplastic polyimide material.

10. The device structure of claim 1 , further comprising external front-side source, drain and gate contact pads provided on an external surface of the support substrate, and low inductance conductive vias extending through the support substrate from said external front-side source, drain and gate contact pads to the conductive metallization layer formed on the support substrate.

11. A method of fabricating the nitride semiconductor device of claim 1 , comprising:
providing a GaN die comprising a silicon growth substrate having formed thereon a GaN epi-layer stack; the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a 2DEG active layer for a lateral GaN transistor and at least one underlying layer;
providing on a front-side of the GaN epi-layer stack, overlying the GaN/AlGaN hetero-layer structure, one or more layers of on-chip metallization defining source and drain electrodes of the lateral GaN transistor, a gate electrode formed on a channel region between the source and drain electrodes of the lateral GaN transistor, and contact pads for said source, drain and gate electrodes;
providing a header comprising a support substrate of dielectric material having a CTE closely matched to the CTE of the GaN epi-layer stack, and a conductive metallization layer formed on the support substrate defining conductive tracks and contact areas for source, drain and gate interconnections, said contact areas for source, drain and gate interconnections having an arrangement for alignment and interconnection with the contact pads for the source, drain and gate electrodes of the GaN transistor;
aligning and assembling the GaN die and the header by providing low inductance conductive interconnections mechanically and electrically interconnecting the contact pads for the source, drain and gate electrodes of the lateral GaN transistor with the contact areas for source, drain and gate interconnections, respectively;
removing the growth substrate from the backside of the epi-layer stack to expose a back-side of the GaN epi-layer stack comprising an underlying buffer layer or intermediate layer of the GaN epi-layer stack, the GaN die then being supported by the header;
providing a conductive layer in direct contact with the back-side of the GaN epi-layer stack, said conductive layer being patterned to de

Assignees

• Gan Systems Inc

Inventors

• Roberts John
• Klowak Greg P
• Mcknight-Macneil Cameron

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W40/10

  Arrangements for heating · CPC title

• H10W40/251

  Organics · CPC title