High-electron-mobility transistor having a buried field plate

Patent metadata

Field	Value
Publication number	US-9728630-B2
Application number	US-201414478287-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Sep 5, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A high-electron-mobility field effect transistor is formed with a buffer region having a stepped lateral profile, the stepped lateral profile having first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section and including a buried field plate, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections. A barrier region is formed along the stepped lateral profile. The barrier region is separated from the buried field plate by a portion of the buffer region. The buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel of a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions.

First claim

What is claimed is:

1. A method of forming a high-electron-mobility field effect transistor, the method comprising:
forming a buffer region having a stepped lateral profile, the stepped lateral profile comprising first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and
forming a buried field plate within the first cross section of the buffer region,
forming a barrier region along the stepped lateral profile of the buffer region, the barrier region separated from the buried field plate by a portion of the buffer region,
wherein the buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material, the first and second semiconductor materials having different band-gaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects,
wherein the buffer region is formed by an epitaxial growth process, and
wherein forming the buried field plate comprises epitaxially growing a second layer of the first or second semiconductor material on a first layer of the first semiconductor material as part of the buffer region,
wherein forming the buffer region and the buried field plate comprises:
growing the first layer of the first semiconductor material;
growing the second layer of the first or second semiconductor material on the first layer;
etching semiconductor material from the first and second layers to form the stepped lateral profile; and
regrowing a third layer of the first semiconductor material along the stepped lateral profile; and
wherein etching semiconductor material comprises removing a lateral portion of the second layer aerial so as to expose an end of the second layer material, wherein regrowing the third layer comprises covering the exposed end of the second layer with regrown first semiconductor material, and wherein forming the barrier region comprises growing a fourth layer of the second semiconductor material over the third layer such that the two-dimensional charge carrier gas is separate from the buried field plate by the regrown third layer of the first semiconductor material.

2. The method of claim 1 , wherein the second layer is a doped conductive layer of the first semiconductor material, and wherein the buried field plate comprises a lateral section of the second layer that remains intact after etching.

3. The method of claim 1 , wherein the second layer is a layer of the second semiconductor material that is configured to be etched selective to the first semiconductor material, and wherein the buried field plate is formed by:
etching the barrier region and the buffer region in the first cross-section so as to expose the second layer, and
etching the second layer selective to the to the first semiconductor material so as to form a buried trench in the buffer region, and
filling the trench with an electrically conductive material.

4. The method of claim 3 , wherein etching the barrier region and the buffer region comprises anisotropic dry etching, and wherein etching the second layer comprises wet chemical etching.

5. The method of claim 1 , further comprising:
forming a gate electrode on the first cross-section over the buried field plate, the gate electrode being spaced apart from the channel by the barrier region;
forming a source electrode on the first cross-section being in ohmic contact with the channel; and
forming a drain electrode outside of the first and third cross-sections being in ohmic contact with the channel.

6. The method of claim 5 , wherein the stepped lateral profile further comprises fourth and fifth cross-sections, the fifth cross-section being substantially equal in thickness to the first cross-section, the fourth cross-section interposed between the fifth and third cross-sections and forming oblique angles with the fifth and third cross-sections, and wherein the drain electrode is formed on the fifth cross-section.

7. The method of claim 1 , further comprising growing a fifth layer of the first semiconductor material on the second layer prior to etching, and wherein etching semiconductor material from the buffer region comprises etching of both the fifth and second layers.

8. A method of forming a high-electron-mobility field effect transistor, the method comprising:
forming a buffer region comprising first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and
forming a buried field plate within the first cross section of the buffer region;
forming a barrier region of substantially uniform thickness along the stepped profile of the buffer region, the barrier region separated from the buried field plate by a portion of the buffer region,
wherein the buffer region is formed from gallium nitride and wherein the barrier region is formed from aluminum gallium nitride such that a two dimensional electron gas forms along the stepped lateral profile near an interface between the barrier region and the buffer region
wherein the buffer region is formed by an epitaxial growth process, and
wherein forming the buried field plate comprises epitaxially growing a second layer of gallium nitride or p-type gallium nitride on a first layer of gallium nitride as part of the buffer region,
wherein forming the buffer region comprises:
growing the layer of gallium nitride and the layer of p-type gallium nitride;
etching a lateral section of the p-type gallium nitride so as to form the stepped lateral profile and expose an end of the layer of p-type gallium nitride; and
regrowing a layer of gallium nitride so as to cover the exposed end with regrown gallium nitride,

wherein forming the barrier region comprises growing aluminum gallium nitride on the regrown gallium nitride, and
wherein the buried field plate comprises a lateral section of the layer of p-type gallium nitride that remains intact after etching.

9. A method of forming a high-electron-mobility field effect transistor, the method comprising:
forming a buffer region having a stepped lateral profile disposed therein, the stepped lateral profile comprising first, second and third cross-sections of the buffer region, the first cross-section being thicker than the third cross-section, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections;
forming a barrier region along the stepped lateral profile of the buffer region,
wherein the buffer region is formed from a first semiconductor material and the barrier region is formed from a second semiconductor material, the first and second semiconductor materials having different band-gaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects, and
forming a buried field plate within the buffer region, the barrier region separated from the buried field plate by a portion of the buffer region,
wherein forming the buried field plate comprises either one of:
(i) epitaxially forming a conductive layer of semiconductor material as part of the buffer region; and
wherein the buried field plate comprises a section of the conductive layer of semicon

Assignees

• Infineon Technologies Austria Ag

Inventors

• Prechtl Gerhard
• Ostermaier Clemens
• Haeberlen Oliver

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/246

  of Group III-V materials · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/66462

  Electricity · mapped topic