Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-12225314-B2
Application number	US-202117995803-A
Country	US
Kind code	B2
Filing date	Apr 9, 2021
Priority date	Apr 17, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An imaging device that has an image processing function and is capable of a high-speed operation is provided. The imaging device has an additional function such as image processing, and can retain analog data obtained by an image capturing operation in pixels and extract data obtained by multiplying the analog data by a given weight coefficient. In the imaging device, the data is stored in a memory cell and pooling processing of data stored in a plurality of memory cells can be performed. The pixels are provided so as to have a region overlapping with at least one of the memory cells, a pooling processing circuit, and a reading circuit of the pixels; thus, an increase in the area of the imaging device can be inhibited even with an additional function.

First claim

The invention claimed is:

1. An imaging device comprising:
a plurality of pixel blocks each comprising a plurality of pixels and a memory cell; and
a first circuit configured to read out a maximum value of the analog data stored in the memory cell included in each of the plurality of pixel blocks,
wherein analog data calculated from data generated by the plurality of pixels is configured to be stored in the memory cell,
wherein the memory cell comprises a sixth transistor, a seventh transistor and a second capacitor, and
wherein one of a source and a drain of the sixth transistor, one electrode of the second capacitor, and a gate of the seventh transistor are electrically connected to each other.

2. The imaging device according to claim 1 , wherein the memory cell includes a region overlapping with at least one of the plurality of pixels and the first circuit.

3. The imaging device according to claim 1 ,
wherein each of the plurality of pixels comprises a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor,
wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one electrode of the first capacitor, and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fifth transistor.

4. The imaging device according to claim 1 ,
wherein each of the sixth transistor and the seventh transistor comprises a metal oxide in a channel formation region, and
wherein the metal oxide includes In, Zn, and one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd and Hf.

5. An electronic device comprising:
the imaging device according to claim 1 ; and
a display device.

6. An imaging device comprising:
a plurality of pixel blocks each comprising a plurality of pixels and a memory cell;
a first circuit;
a second circuit; and
a third circuit,
wherein each of the plurality of pixels is configured to:
retain first data corresponding to a reset operation;
retain second data corresponding to a photoelectric conversion operation;
generate third data by adding a weight coefficient and the first data; and
generate fourth data by adding the weight coefficient and the second data,

wherein the first circuit is configured to:
generate fifth data corresponding a difference between a sum of the first data retained in the plurality of pixels and a sum of the third data generated in the plurality of pixels; and
generate sixth data corresponding a difference between a sum of the second data retained in the plurality of pixels and a sum of the fourth data generated in the plurality of pixels,

wherein the second circuit is configured to generate seventh data corresponding a difference between the fifth data and the sixth data,
wherein the memory cell is configured to store the seventh data, and
wherein the third circuit is configured to read out a maximum value of the seventh data stored in the memory cell included in each of the plurality of pixel blocks.

7. The imaging device according to claim 6 ,
wherein each of the plurality of pixels comprises a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor,
wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one electrode of the first capacitor, and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fifth transistor.

8. The imaging device according to claim 6 ,
wherein the memory cell comprises a sixth transistor, a seventh transistor and a second capacitor, and
wherein one of a source and a drain of the sixth transistor, one electrode of the second capacitor, and a gate of the seventh transistor are electrically connected to each other.

9. The imaging device according to claim 8 ,
wherein each of the sixth transistor and the seventh transistor comprises a metal oxide in a channel formation region, and
wherein the metal oxide includes In, Zn, and one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd and Hf.

10. The imaging device according to claim 6 , wherein each of the first circuit and the second circuit is a correlated double sampling circuit.

11. The imaging device according to claim 6 , wherein the third circuit comprises a plurality of current mirror circuits.

12. The imaging device according to claim 6 , wherein each of the first circuit, the second circuit and the third circuit comprises a transistor including silicon in a channel formation region.

13. The imaging device according to claim 6 , wherein the plurality of pixels include a region overlapping with at least one of the first circuit, the second circuit and the third circuit.

14. The imaging device according to claim 6 , wherein the memory cell includes a region overlapping with at least one of the first circuit, the second circuit, the third circuit and the plurality of pixels.

15. An electronic device comprising:
the imaging device according to claim 6 ; and
a display device.

Assignees

• Semiconductor Energy Lab

Inventors

• Yoneda Seiichi
• Negoro Yusuke
• Hirose Takeya
• Sato Shunsuke
• Yamazaki Shunpei

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10F39/803

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H10K39/32

  Organic image sensors · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title