Semiconductor device package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12224481-B2
Application number	US-202318118738-A
Country	US
Kind code	B2
Filing date	Mar 7, 2023
Priority date	Jul 9, 2019
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a substrate; and
an antenna module disposed over the substrate, the antenna module comprising:
a supporting element;
an antenna pattern disposed over the supporting element;
a pad;
a conductive pillar penetrating the supporting element and electrically connecting the antenna pattern to the pad;
a first dielectric layer disposed below the supporting element and having an opening; and
an electrical contact partially disposed within the opening of the first dielectric layer, and connecting the pad and the substrate,
wherein a lower surface of the pad is exposed from the opening of the first dielectric layer, and the pad directly contacts the conductive pillar and the electrical contact.

2. The semiconductor device package of claim 1 , wherein the antenna module includes a second dielectric layer in contact with lateral surfaces of the antenna pattern, wherein the second dielectric layer includes a portion vertically overlapping the antenna pattern in a cross-sectional view, wherein a thickness of the portion of the second dielectric layer is less than a thickness of antenna pattern.

3. The semiconductor device package of claim 1 , wherein the antenna pattern includes a first portion and a second portion separated from the first portion by a third dielectric layer, wherein a width of the first portion is different from a width of the second portion in a cross-sectional view.

4. The semiconductor device package of claim 3 , wherein the antenna pattern further includes a third portion separated from the first portion and the second portion by the third dielectric layer, wherein the first portion is between the second portion and the third portion, and wherein the width of the first portion is different from a width of the third portion.

5. The semiconductor device package of claim 4 , wherein a horizontal distance between the first portion and the second portion of the antenna pattern is different from a horizontal distance between the first portion and the third portion of the antenna pattern.

6. The semiconductor device package of claim 3 , further comprising an electronic component disposed under the substrate and vertically overlapping the first portion and the second portion of the antenna pattern.

7. A semiconductor device package, comprising:
a substrate;
a first antenna module disposed over the substrate, the first antenna module including:
a supporting element;
an antenna pattern disposed over the supporting element, wherein the antenna pattern has a first lateral surface non-perpendicular to a top surface of the substrate in a cross-sectional view;
a conductive pillar within the supporting element; and
a conductive layer disposed between the antenna pattern and the supporting element and connecting the conductive pillar to the antenna pattern; and

a second antenna module disposed over the substrate and spaced apart from the first antenna module.

8. The semiconductor device package of claim 7 , wherein the antenna pattern has a second lateral surface opposite to and non-parallel to the first lateral surface.

9. The semiconductor device package of claim 7 , wherein a first width of the antenna pattern at a first elevation is less than a second width of the antenna pattern at a second elevation in a cross-sectional view, wherein the second elevation is lower than the first elevation with respect to the substrate.

10. The semiconductor device package of claim 7 , wherein the conductive pillar is electrically connected to a feeding point of the antenna pattern for signal transmission.

Assignees

• Advanced Semiconductor Eng

Inventors

• Ho Cheng-Lin
• Lee Chih-Cheng
• Chen Chun Chen
• Yu Yuanhao

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title