Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12224277-B2
Application number	US-202318149206-A
Country	US
Kind code	B2
Filing date	Jan 3, 2023
Priority date	Dec 27, 2019
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

First claim

What is claimed is:

1. A memory device, comprising:
a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
an upper substrate, and
a memory cell array on the upper substrate and including a first memory block; and

a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
a lower substrate, and
an address decoder on the lower substrate and configured to control the memory cell array,

wherein the first memory block includes
a first core region including first memory cells, and
a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,

wherein the first extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,

wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
wherein a quantity of step zones in the first extension region is equal to a quantity of flat zones in the first extension region.

2. The memory device of claim 1 , wherein:
the plurality of step zones include a first step zone and a second step zone that extend sequentially in a first series pattern along the first direction,
the at least one flat zone includes a first flat zone and a second flat zone that extend sequentially in a second series pattern along the first direction,
the first flat zone is between the first step zone and the second step zone, and
the second step zone is between the first flat zone and the second flat zone.

3. The memory device of claim 2 , wherein:
the memory cell array further includes a second memory block,
the first memory block and the second memory block extend sequentially in a serial pattern along the second direction, and
the second memory block includes
a second core region including second memory cells, and
a second extension region adjacent to a first side of the second core region, the second extension region including a plurality of wordline contacts configured to establish an electrical connection with the plurality of wordlines.

4. The memory device of claim 3 , wherein:
the second extension region includes
a first wordline step zone and a second wordline step zone that extend sequentially in the first series pattern along the first direction, and
a first wordline flat zone and a second wordline flat zone that extend sequentially in the second series pattern along the first direction,

the first wordline flat zone is between the first wordline step zone and the second wordline step zone, and
the second wordline step zone is between the first wordline flat zone and the second wordline flat zone.

5. The memory device of claim 4 , wherein:
the plurality of wordline contacts include first wordline contacts in the first wordline step zone and second wordline contacts in the second wordline step zone,
the plurality of through-hole vias include first through-hole vias in the first flat zone and second through-hole vias in the second flat zone,
the first wordline contacts are connected to the first through-hole vias, and
the second wordline contacts are connected to the second through-hole vias.

6. The memory device of claim 4 , wherein:
the first step zone and the first wordline step zone are aligned along the second direction,
the second step zone and the second wordline step zone are aligned along the second direction,
the first flat zone and the first wordline flat zone are aligned along the second direction, and
the second flat zone and the second wordline flat zone are aligned along the second direction.

7. The memory device of claim 2 , wherein, among the plurality of through-hole vias, a first quantity of through-hole vias in the first flat zone is equal to a second quantity of through-hole vias in the second flat zone.

8. The memory device of claim 7 , wherein:
a size of the first flat zone is equal to a size of the second flat zone, and
a size of the first step zone is equal to a size of the second step zone.

9. The memory device of claim 2 , wherein, among the plurality of through-hole vias, a first quantity of through-hole vias in the first flat zone is different from a second quantity of through-hole vias in the second flat zone.

10. The memory device of claim 9 , wherein:
a size of the first flat zone is greater than a size of the second flat zone, and
the first quantity is greater than the second quantity.

11. The memory device of claim 9 , wherein:
a size of the first step zone is greater than a size of the second step zone, and
the first quantity is greater than the second quantity.

12. A memory device, comprising:
a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
an upper substrate, and
a memory cell array on the upper substrate and including a first memory block; and

a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
a lower substrate, and
an address decoder on the lower substrate and configured to control the memory cell array,

wherein the first memory block includes
a first core region including first memory cells, and
a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,

wherein the first extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,

wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
wherein a quantity of step zones in the first extension region is greater than a quantity of flat zones in the first extension region.

13. The memory device of claim 12 , wherein:
the plurality of step zones include a first step zone and a second step zone that extend sequentially in a first series pattern along the first direction, and
the at least one flat zone includes a first flat zone between the first step zone and the second step zone.

14. The memory device of claim 13 , wherein:
the memory cell array further includes a second memory block,
the first memory block and the second memory block extend sequentially in a serial pattern along the second direction, and
the second memory block includes
a second core region including second memory cells, and
a second extension region adjacent to a first side of the second core region, the second extension region including a plurality of wordline contacts configured to establish an

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yonghyuk
• Lim Bongsoon
• Jeon Hongsoo
• Yu Jaeduk

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title