Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof

Patent metadata

Field	Value
Publication number	US-10256248-B2
Application number	US-201615175450-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Jun 7, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region. At least one through-memory-level via structure can be formed through the remaining portions of the spacer dielectric layers and the insulating layers to provide a vertically conductive path through a memory-level assembly.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a memory-level assembly located over a semiconductor substrate and comprising an alternating stack of insulating layers and spacer dielectric layers having portions thereof replaced with electrically conductive layers, wherein a respective spacer dielectric layer and a respective electrically conductive layer are laterally adjoined to each other, and wherein each spacer dielectric layer within the alternating stack other than a bottommost one of the spacer dielectric layers within the alternating stack has a greater lateral extent than any overlying one of the spacer dielectric layers within the alternating stack;
a retro-stepped dielectric material portion overlying, and contacting, stepped surfaces of the alternating stack;
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises:
a vertical semiconductor channel; and
a memory film comprising a tunneling dielectric and charge storage regions; and

at least one through-memory-level via structure consisting of at least one conductive material and vertically extending through the retro-stepped dielectric material portion, a respective subset of the spacer dielectric layers within the alternating stack, and a respective subset of the insulating layers within the alternating stack, and is laterally spaced from each of the electrically conductive layers within the alternating stack.

2. The semiconductor structure of claim 1 , wherein:
the spacer dielectric layers of the alternating stack comprise concave substantially vertical sidewalls; and
the concave substantially vertical sidewalls of spacer dielectric layers are vertically coincident among one another.

3. The semiconductor structure of claim 2 , wherein each of the concave substantially vertical sidewalls of the spacer dielectric layers contacts, or is uniformly spaced from, a respective convex substantially vertical sidewall of the electrically conductive layers.

4. The semiconductor structure of claim 3 , further comprising:
backside contact trenches vertically extending through the memory-level assembly, and laterally extending along a first horizontal direction; and
laterally-elongated contact via structures that are located within a respective one of the backside contact trenches,
wherein:
the concave substantially vertical sidewalls of the spacer dielectric layers are substantially equidistant from a sidewall of one of the backside contact trenches.

5. The semiconductor structure of claim 4 , wherein at least two of the concave substantially vertical sidewalls of the spacer dielectric layers contact at least two convex substantially vertical sidewalls of the electrically conductive layers of the alternating stack at substantially vertical interfaces.

6. The semiconductor structure of claim 2 , wherein one of the spacer dielectric layers comprises a first planar substantially vertical sidewall and a second planar substantially vertical sidewall that laterally extend along a first horizontal direction and laterally spaced apart by a width of the one of the spacer dielectric layers along a second horizontal direction that is perpendicular to the first horizontal direction.

7. The semiconductor structure of claim 6 , further comprising:
backside contact trenches vertically extending through the memory-level assembly, and laterally extending along a first horizontal direction; and
laterally-elongated contact via structures that are located within a respective one of the backside contact trenches,
wherein:
each of the first planar substantially vertical sidewall and the second planar substantially vertical sidewall is laterally spaced from a sidewall of one of the backside contact trenches by a substantially same lateral offset distance; and
the one of the spacer dielectric layers comprises a concave substantially vertical sidewall that is adjoined to the first planar substantially vertical sidewall and the second planar substantially vertical sidewall.

8. The semiconductor structure of claim 1 , wherein
the alternating stack includes stepped surfaces that contact bottom surfaces and sidewall surfaces of the respective retro-stepped dielectric material portion.

9. The semiconductor structure of claim 1 , further comprising:
a planar semiconductor material layer underlying the memory-level assembly, and including horizontal semiconductor channels electrically connected to, and directly contacting bottom ends of, vertical semiconductor channels within the memory stack structures; and
at least one lower level dielectric layer underlying an entirety of a bottom surface of the planar semiconductor material layer and overlying the semiconductor substrate,
wherein each of the at least one through-memory-level via structure comprises a respective bottom surface that is located below a horizontal Wane including the bottom surface of the planar semiconductor material layer.

10. The semiconductor structure of claim 9 , wherein each of the at least one through-memory-level via structure directly contacts a metallic top surface of a respective lower level metal interconnect structure underlying a horizontal plane including a bottommost surface of the memory-level assembly and laterally surrounded by the at least one lower level dielectric layer, and directly contacts a metallic bottom surface of a respective upper level metal interconnect structure overlying a horizontal plane including a topmost surface of the memory-level assembly.

11. The semiconductor structure of claim 9 , further comprising driver circuit semiconductor devices located on the semiconductor substrate, comprising source regions and drain regions embedded within an upper portion of the semiconductor substrate, and vertically spaced apart from, and located below, the planar semiconductor material layer, wherein a lower level metal interconnect structure is electrically shorted to at least one node of the semiconductor devices, and is embedded in the at least one lower level dielectric layer.

12. The semiconductor structure of claim 11 , further comprising word line contact via structures which are electrically shorted to a respective one of the electrically conductive layers in the alternating stack.

13. The semiconductor structure of claim 12 , further comprising:
an upper level metal interconnect structure that is electrically shorted to one of the word line contact via structures and one of the at least one through-memory-level via structure; and
driver circuit semiconductor devices located on the semiconductor substrate and comprising source regions and drain regions embedded within an upper portion of the semiconductor substrate and comprising word line switching semiconductor devices,
wherein:
the electrically conductive layers of the alternating stack comprise word lines of a NAND memory device; and
one of the word line switching semiconductor devices is electrically shorted to one of the word lines through the lower level metal interconnect structure, one of the at least one through-memory-level via structure, one of the upper level metal interconnect structures, and the one of the word line contact via structures.

14. The semiconductor structure of claim 1 , wherein:
the memory stack structures comprises memory elements of a vertical NAND device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the semiconductor substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensiona

Assignees

• Sandisk Technologies Llc

Inventors

• Lu Zhenyu
• Yu Jixin
• Alsmeier Johann
• Toyama Fumiaki
• Mizutani Yuki
• Ogawa Hiroyuki
• Ge Chun
• Mao Daxin
• Zhang Yanli
• Chu Alexander
• Li Yan

Classifications

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title