Through-memory-level via structures for a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10038006-B2
Application number	US-201615269294-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Dec 22, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a memory-level assembly located over a semiconductor substrate and comprising at least one first alternating stack of electrically conductive layers and first portions of insulating layers, and further comprising memory stack structures vertically extending through the at least one first alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel, wherein the electrically conductive layers comprise word lines for the memory stack structures;
an insulating moat trench structure vertically extending through the memory-level assembly and defining an area of a through-memory-level via region laterally spaced from the at least one first alternating stack;
at least one second alternating stack located in the through-memory-level via region, wherein the at least one second alternating stack includes alternating layers of dielectric spacer layers and second portions of the insulating layers, and each of the dielectric spacer layers is located at a same level as a respective electrically conductive layer; and
through-memory-level via structures located within the through-memory-level via region and comprising a conductive material.

2. The semiconductor structure of claim 1 , wherein:
the area of the through-memory-level via region comprises an area within a closed inner periphery of the insulating moat trench structure; and
the through-memory-level via structures vertically extend from a first horizontal plane including a topmost surface of the memory-level assembly and a bottommost surface of the memory-level assembly.

3. The semiconductor structure of claim 1 , further comprising a plurality of laterally-elongated contact via structures extending along a first horizontal direction laterally divides the memory-level assembly into a plurality of laterally spaced-apart blocks.

4. The semiconductor structure of claim 3 , wherein:
the plurality of blocks comprises a set of at least three neighboring blocks including, in order, a first block, a second block, and third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction; and
the insulating moat trench structure is located on a lengthwise end of the second block and between a staircase region of the first block and a staircase region of the third block, each staircase region of the first and third blocks including terraces in which each underlying electrically conductive layer extends farther along the first horizontal direction than any overlying electrically conductive layer within the memory-level assembly.

5. The semiconductor structure of claim 4 , wherein stepped bottom surfaces of a retro-stepped dielectric material portion contacts stepped top surfaces of the staircase regions of the first and third blocks.

6. The semiconductor structure of claim 5 , wherein stepped bottom surfaces of an additional retro-stepped dielectric material portion comprising a same material as the retro-stepped dielectric material portion and laterally spaced from the retro-stepped dielectric material portion by the insulating moat trench structure contact stepped top surfaces of the at least one second alternating stack.

7. The semiconductor structure of claim 3 , wherein:
each of the plurality of laterally-elongated contact via structures is laterally surrounded by an insulating spacer; and
the insulating moat trench structure comprises an insulating liner comprising a same material as the memory film.

8. The semiconductor structure of claim 7 , wherein the insulating moat structure comprises a layer stack including a same set of layers as layers included in each of the memory stack structures.

9. The semiconductor structure of claim 3 , wherein:
each of the plurality of laterally-elongated contact via structures is laterally surrounded by an insulating spacer; and
the insulating moat trench structure comprises an insulating liner comprising a same material as the an insulating spacer.

10. The semiconductor structure of claim 9 , wherein the insulating moat trench structure comprises a conductive fill portion comprising a same conductive material as the plurality of laterally-elongated contact via structures.

11. The semiconductor structure of claim 3 , wherein the plurality of laterally-elongated contact via structures comprises source lines contacting respective underlying source regions that contact respective horizontal channels.

12. The semiconductor structure of claim 1 , wherein the insulating moat structure consists essentially of a dielectric fill material portion.

13. The semiconductor structure of claim 1 , further comprising:
semiconductor devices located on the semiconductor substrate;
lower level metal interconnect structures electrically shorted to nodes of the semiconductor devices and embedded in at least one lower level dielectric layer that overlies the semiconductor substrate; and
a planar semiconductor material layer overlying the at least one lower level dielectric layer and including horizontal semiconductor channels connected to vertical semiconductor channels within the memory stack structures.

14. The semiconductor structure of claim 13 , further comprising upper level metal interconnect structures overlying the memory-level assembly, electrically coupled to the respective word lines, and embedded in at least one upper level dielectric layer,
wherein the through-memory-level via structures vertically extend through the memory-level assembly and contact respective pairs of an upper level metal interconnect structure and a lower level metal interconnect structure; and
wherein the semiconductor devices comprise word line switch devices.

15. The semiconductor structure of claim 1 , wherein:
the memory stack structures comprise memory elements of a vertical NAND device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the semiconductor substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

16. A method of forming a semiconductor structure, comprising:
forming at least one alternating stack of insulating layers and dielectric spacer layers over a semiconductor substrate;
forming memory stack structures through the at least one alternating sta

Assignees

• Sandisk Technologies Llc

Inventors

• Furihata Yoko
• Yu Jixin
• Ogawa Hiroyuki
• Kai James
• Liu Jin
• Alsmeier Johann

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title