Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12224183-B2
Application number	US-202217896171-A
Country	US
Kind code	B2
Filing date	Aug 26, 2022
Priority date	Nov 2, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

First claim

What is claimed is:

1. A method of manufacturing semiconductor device comprising the steps of:
providing a package including a first carrier, a seed layer, a plurality of wires, a die and a molding material, the seed layer is formed on the first carrier, the plurality of wires are formed on the seed layer, the die is bonded to the plurality of wires, and the die and the plurality of wires are covered by the molding material;
disposing a second carrier on the molding material;
removing the first carrier to expose the seed layer;
removing the seed layer to expose the plurality of wires; and
depositing a gold layer on each of the plurality of wires by immersion gold plating.

2. The method of manufacturing semiconductor device in accordance with claim 1 , wherein each of the plurality of wires includes a nickel layer and a copper layer, the nickel layer is formed on the seed layer by pure nickel electroplating, the copper layer is formed on the nickel layer, the nickel layer is exposed after removing the seed layer, and the gold layer is deposited on the nickel layer by immersion gold plating.

3. The method of manufacturing semiconductor device in accordance with claim 2 , wherein the copper layer is a redistribution layer.

4. The method of manufacturing semiconductor device in accordance with claim 1 , wherein each of the plurality of wires includes a copper layer which is formed on the seed layer, the copper layer is exposed after removing the seed layer, and the gold layer is deposited on the copper layer by immersion gold plating.

5. The method of manufacturing semiconductor device in accordance with claim 4 , wherein the copper layer is a redistribution layer.

6. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the seed layer is removed by plasma etching.

7. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, and a top surface and a lateral surface of each of the plurality of wires are exposed after removing the seed layer and a top part of the patterned dielectric layer by plasma etching.

8. The method of manufacturing semiconductor device in accordance with claim 7 , wherein the gold layer is deposited on the top surface and the lateral surface of each of the plurality of wires.

9. The method of manufacturing semiconductor device in accordance with claim 7 , wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

10. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, each of the plurality of wires includes a nickel layer and a copper layer, the nickel layer is formed on the seed layer by pure nickel electroplating, the copper layer is formed on the nickel layer, a top surface and a lateral surface of the nickel layer are exposed after removing the seed layer and a top part of the pattern dielectric layer by plasma etching.

11. The method of manufacturing semiconductor device in accordance with claim 10 , wherein the gold layer is deposited on the top surface and the lateral surface of the nickel layer.

12. The method of manufacturing semiconductor device in accordance with claim 10 , wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

13. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the plurality of wires are formed on the seed layer using a patterned dielectric layer, each of the plurality of wires includes a copper layer which is formed on the seed layer, a top surface and a lateral surface of the copper layer are exposed after removing the seed layer and a top part of the patterned dielectric layer by plasma etching.

14. The method of manufacturing semiconductor device in accordance with claim 13 , wherein the gold layer is deposited on the top surface and the lateral surface of the copper layer.

15. The method of manufacturing semiconductor device in accordance with claim 13 , wherein a removed thickness of the patterned dielectric layer is less than or equal to 1.5 μm.

16. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the first carrier includes a substrate and a release layer which is located on the substrate, the seed layer is formed on the release layer and exposed after removing the substrate and the release layer.

17. The method of manufacturing semiconductor device in accordance with claim 1 , wherein the seed layer is a titanium-tungsten/copper layer or a titanium/copper layer.

18. The method of manufacturing semiconductor device in accordance with claim 1 , wherein a solder ball is formed on the gold layer after depositing the gold layer.

Assignees

• Chipbond Technology Corp

Inventors

• Jenq Shrane-Ning
• Hsu Wen-Cheng
• Wang Chen-Yu
• Kuo Chih-Ming
• Chen Chwan-Tyaw
• Ho Lung-Hua

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title