RDL-first packaging process

Patent metadata

Field	Value
Publication number	US-9425178-B2
Application number	US-201414325842-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.

First claim

What is claimed is:

1. A method comprising:
forming a first plurality of Redistribution Lines (RDLs) over a carrier, wherein the forming the first plurality of RDLs comprises:
forming a metal seed layer over a release layer, with the release layer being over the carrier;
forming a dielectric layer over the metal seed layer;
patterning the dielectric layer to reveal portions of the metal seed layer; and
performing a plating to form the first plurality of RDLs;

bonding a device die to the first plurality of RDLs through flip-chip bonding, wherein the device die and the first plurality of RDLs are over the carrier;
molding the device die in a molding material;
after the molding, detaching the carrier from the first plurality of RDLs; and
forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.

2. The method of claim 1 further comprising forming a plurality of through-vias electrically coupled to the first plurality of RDLs, wherein during the molding, the plurality of through-vias are molded in the molding material.

3. The method of claim 2 further comprising, after the forming the solder balls, grinding the molding material to reveal the plurality of through-vias.

4. The method of claim 2 further comprising:
before the forming the solder balls and before the detaching the carrier, grinding the molding material to reveal the plurality of through-vias; and
after the grinding the molding material and before the detaching the carrier, forming a plurality of solder regions on the plurality of through-vias.

5. The method of claim 2 further comprising:
plating a plurality of solder regions over the plurality of through-vias, with edges of the plurality of solder regions aligned to respective edges of the plurality of through-vias; and
grinding the molding material to reveal the plurality of solder regions.

6. The method of claim 2 further comprising:
after the molding the device die and before the detaching the carrier, grinding the molding material to reveal the plurality of through-vias; and
forming a second plurality of RDLs to electrically couple to the plurality of through-vias, wherein the first plurality of RDLs and the second plurality of RDLs are on opposite sides of the molding material.

7. The method of claim 1 , wherein the device die comprises additional through-vias and metal pillars electrically connected to the additional through-vias, and wherein the method further comprises:
after the molding the device die, grinding the device die and the molding material to reveal the metal pillars; and
bonding a die stack to the metal pillars of the device die.

8. The method of claim 1 further comprising:
after the molding the device die and the detaching the carrier, forming a plurality of through-vias electrically coupled to the first plurality of RDLs;
bonding a die stack to the first plurality of RDLs, wherein the plurality of through-vias and the die stack are on an opposite side of the first plurality of RDLs than the device die;
molding the plurality of through-vias and the die stack in an additional molding material; and
grinding the additional molding material to reveal the plurality of through-vias.

9. The method of claim 1 , wherein the forming the dielectric layer comprises forming a polymer layer.

10. The method of claim 1 further comprising performing a singulation to saw a plurality of dielectric layers, with the first plurality of RDLs in the plurality of dielectric layers.

11. A method comprising:
forming a metal seed layer over a carrier;
forming a dielectric layer over the metal seed layer;
patterning the dielectric layer to reveal portions of the metal seed layer;
forming a first plurality of RDLs, with the first plurality of RDLs comprising first portions extending into the dielectric layer, and second portions over the dielectric layer;
forming a second plurality of RDLs over and electrically coupled to the first plurality of RDLs;
bonding a device die to the second plurality of RDLs through flip-chip bonding, wherein the device die comprises:
a semiconductor substrate; and
a plurality of through-vias and metal pillars electrically connected to the additional through-vias;

molding the device die in a molding material;
grinding the molding material and the device die to reveal the metal pillars; and
performing a singulation to form a plurality of packages, with the device die in one of the plurality of packages.

12. The method of claim 11 further comprising:
before the grinding the molding material, removing the carrier and the metal seed layer; and
forming solder regions to electrically couple to the first plurality RDLs, with the solder regions and the device die being on opposite sides of the first plurality RDLs.

13. The method of claim 11 further comprising, after the patterning the dielectric layer and before the forming the first plurality of RDLs, plating a plurality of Under-Bump Metallurgies (UBMs) in openings of the dielectric layer.

14. The method of claim 13 , wherein the plating the plurality of UBMs comprises selective plating.

15. The method of claim 11 , wherein the forming the dielectric layer comprises forming a polymer layer.

16. The method of claim 11 further forming a release layer over the carrier, wherein the metal seed layer is formed over the release layer, and the method further comprises removing the release layer and the carrier from the dielectric layer and the first plurality of RDLs.

17. The method of claim 11 further comprising bonding an additional device die to the second plurality of RDLs through flip-chip bonding, wherein after the grinding, the second device die remains to be covered by a portion of the molding material.

18. A method comprising:
forming a metal seed layer over a carrier layer;
forming a dielectric layer over the metal seed layer;
patterning the dielectric layer to form openings, with portions of the metal seed layer revealed through the openings;
forming a first plurality of RDLs, wherein portions of the plurality of RDLs extend into the openings;
forming a second plurality of RDLs over and electrically coupled to the first plurality of RDLs;
bonding a device die to the second plurality of RDLs through flip-chip bonding;
forming a plurality of through-vias on the second plurality of RDLs;
molding the plurality of through-vias and the device die in a molding material;
after the molding, detaching the carrier from the first plurality of RDLs;
forming a plurality of solder regions electrically coupled to the first plurality of RDLs, with the plurality of solder regions and the device die being on opposite sides of the first plurality of RDLs;
after the detaching the carrier and the forming the plurality of solder regions, grinding the molding material to reveal the plurality of through-vias; and
performing a singulation to form a plurality of packages, with the device die in one of the plurality of packages.

19. The method of claim 18 further comprising selectively plating Under-Bump Metallurgies in the openings, wherein the first plurality of RDLs is formed on the Under-Bump Metallurgies.

20. The method of claim 18 , wherein the forming the dielectric layer comprises forming a polymer layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Wei
• Chen Shing-Chao
• Chen Meng-Tse
• Cheng Ming-Da
• Liu Chung-Shi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title