Decimal floating-point instruction in a round-for-reround mode

Patent metadata

Field	Value
Publication number	US-12223290-B2
Application number	US-202318338901-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Mar 1, 2007
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A decimal floating-point instruction is executed in a round-for-reround mode. The decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand. The executing includes forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion. The high order portion has a least significant digit. A rounded-for-reround number is created from the intermediate result. The rounded-for-reround number includes the high order portion of the intermediate result and based on the least significant coefficient digit of the high order portion being a selected value and based on the low order portion having another selected value, the least significant digit of the rounded-for-reround number is incremented. The rounded-for-reround number is stored.

First claim

What is claimed is:

1. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:
executing, by a computer processor of the computing environment, a decimal floating-point instruction in a round-for-reround mode, wherein the computer processor is part of a machine that includes one or more floating point registers and wherein the decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand, the executing the decimal floating-point instruction comprising:
forming, by the computer processor, based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion, the high order portion having a least significant digit;
creating from the intermediate result a rounded-for-reround number, the rounded-for-reround number comprising the high order portion of the intermediate result, and wherein based on the least significant digit of the high order portion being a selected value and based on the low order portion having another selected value, incrementing the least significant digit of the rounded-for-reround number; and
storing in a selected location, by the computer processor, the rounded-for-reround number.

2. The computer-implemented method of claim 1 , wherein based on the rounded-for-reround number having a predefined least significant digit, the rounded-for-reround number is exact.

3. The computer-implemented method of claim 2 , wherein based on the rounded-for-reround number having the predefined least significant digit, the rounded-for-reround number is exact and the low order portion is a certain value.

4. The computer-implemented method of claim 3 , wherein the certain value is zero.

5. The computer-implemented method of claim 1 , wherein the selected value is zero.

6. The computer-implemented method of claim 1 , wherein the selected value is five.

7. The computer-implemented method of claim 1 , wherein the another selected value is a value other than zero.

8. The computer-implemented method of claim 1 , wherein the rounded-for-reround number is a decimal floating-point number.

9. The computer-implemented method of claim 1 , further comprising:
executing a decimal floating-point reround instruction, the executing the decimal floating-point reround instruction comprising:
rounding the rounded-for-reround number to produce a rounded result; and
storing the rounded result as a result of executing the decimal floating-point reround instruction.

10. The computer-implemented method of claim 9 , wherein the intermediate result has a number of decimal coefficient digits of precision, and wherein the rounded result represents a decimal floating-point number having at least one fewer decimal coefficient digits of precision than the number of decimal coefficient digits of precision of the intermediate result.

11. The computer-implemented method of claim 1 , wherein the decimal floating-point operand is fetched by an execution unit of the computer processor.

12. The computer-implemented method of claim 1 , further comprising fetching the decimal floating-point instruction in the machine, the machine implementing a plurality of floating-point registers.

13. The computer-implemented method of claim 1 , further comprising:
executing another instance of the decimal floating-point instruction in the round-for-reround mode, wherein the another instance of the decimal floating-point instruction is configured to perform another decimal floating-point operation on another decimal floating-point operand, the executing the another instance of the decimal floating-point instruction comprising:
forming another intermediate result having another high order portion and another low order portion, the another high order portion having another least significant digit;
creating from the another intermediate result another rounded-for-reround number, the creating the another rounded-for-reround number comprising based on the another low order portion being a particular value, leaving the another least significant digit of the another intermediate result unchanged; and
storing the another rounded-for-reround number.

14. The computer-implemented method of claim 13 , wherein the particular value is zero.

15. A computer system for facilitating processing within a computing environment, the computer system comprising:
a memory; and
one or more computer processors in communication with the memory, the one or more computer processors being part of a machine that includes one or more floating point registers, and wherein the computer system is configured to perform a method, said method comprising:
executing a decimal floating-point instruction in a round-for-reround mode, wherein the decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand, the executing the decimal floating-point instruction comprising:
forming based on performing the decimal floating-point operation, an intermediate result having a high order portion and a low order portion, the high order portion having a least significant digit;
creating from the intermediate result a rounded-for-reround number, the rounded-for-reround number comprising the high order portion of the intermediate result, and wherein based on the least significant digit of the high order portion being a selected value and based on the low order portion having another selected value, incrementing the least significant digit of the rounded-for-reround number; and
storing in a selected location the rounded-for-reround number.

16. The computer system of claim 15 , wherein based on the rounded-for-reround number having a predefined least significant digit, the rounded-for-reround number is exact.

17. The computer system of claim 16 , wherein based on the rounded-for-reround number having the predefined least significant digit, the rounded-for-reround number is exact and the low order portion is a certain value.

18. The computer system of claim 15 , wherein the method further comprises:
executing a decimal floating-point reround instruction, the executing the decimal floating-point reround instruction comprising:
rounding the rounded-for-reround number to produce a rounded result; and
storing the rounded result as a result of executing the decimal floating-point reround instruction.

19. The computer system of claim 18 , wherein the intermediate result has a number of decimal coefficient digits of precision, and wherein the rounded result represents a decimal floating-point number having at least one fewer decimal coefficient digits of precision than the number of decimal coefficient digits of precision of the intermediate result.

20. A computer program product for facilitating processing within a computing environment, said computer program product comprising:
one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media readable by at least one processing circuit to:
execute, by a computer processor, a decimal floating-point instruction in a round-for-reround mode, wherein the computer processor is part of a machine that includes one or more floating point registers and the decimal floating-point instruction is configured to perform a decimal floating-point operation on a decimal floating-point operand, and wherein execution of the decimal floating-

Assignees

• IBM

Inventors

• Schwarz Eric Mark
• Schmookler Martin Stanley

Classifications

• G06F7/49984

  Rounding away from zero · CPC title

• G06F7/49978

  Rounding towards zero (G06F7/49957 takes precedence) · CPC title

• G06F7/49973

  Rounding towards negative infinity, e.g. truncation of two's complement numbers (G06F7/49957 takes precedence) · CPC title

• G06F7/49963

  Rounding to nearest (G06F7/49957 takes precedence) · CPC title

• G06F7/49947

  Rounding · CPC title