Round for reround mode in a decimal floating point instruction

Patent metadata

Field	Value
Publication number	US-9690544-B2
Application number	US-201514943254-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Mar 1, 2007
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

First claim

What is claimed is:

1. A computer system for executing a machine instruction in a central processing unit, the machine instruction being defined for computer execution according to a computer architecture, the system comprising:
an instruction fetching unit for fetching instructions to be executed;
a floating point arithmetic unit for executing floating point operations of fetched floating point instructions; and
an operand storage in communication with said floating point arithmetic unit;

wherein the computer system performs a method comprising:
a) executing, by a computer processor, a decimal floating point instruction configured to perform a decimal floating point operation, the decimal floating point instruction configured to utilize a round-for-reround mode, the executing step comprising:
producing, by the computer processor, an intermediate result of the executed decimal floating point operation, the intermediate result having a high order portion and a low order portion, the high order portion corresponding to a hardware format, the hardware format having a first number of digits of precision including a least significant digit;
rounding, by an Arithmetic Unit (AU), the high order portion according to the round-for-reround mode, wherein:
based on the least significant bit of the high order portion being 0 and based on the value of the low order portion being greater than 0, changing the least significant bit of said high order portion to 1 to form a to-be-stored high order portion; and
based on the least significant bit of the high order portion of the intermediate result produced being 1, or based on the value of the low order portion of said intermediate result produced being 0, leaving the least significant digit of said high order portion unchanged to form said to-be-stored high order portion;

storing, in a computer processor storage unit, the to-be-stored high order portion as a final result of the executed decimal floating point operation; and

b) subsequent to execution of the decimal floating point instruction, executing, by the computer processor, a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to any of a plurality of rounding precisions, executing the decimal reround instruction execution comprising:
fetching, by the processor, the stored final result of the executed decimal floating point operation, the fetched final result having a first number of bits representing a first number of decimal digits;
determining a decimal reround instruction specified rounding precision of the plurality of rounding precisions, wherein the specified rounding precision employs a second number of digits consisting of two or more fewer digits than the first number of digits;
rounding, by the AU, the fetched final result to the second number of digits specified by the decimal reround interaction; and
storing, in a computer processor storage unit, the rounded final result of the executed decimal floating point operation as a result of the decimal reround instruction.

2. The system according to claim 1 , wherein the method further comprises pre-rounding, by the computer processor, the high order portion according to a pre-round mode, wherein the pre-rounding mode comprises any one of round toward 0, round away from 0, round toward +infinity, round toward −infinity, round to nearest with ties to even, round to nearest with ties toward 0 and round to nearest with ties away from 0.

3. The system according to claim 1 , wherein the operands of the decimal floating point instruction are encoded forms of decimal numbers, wherein the encoded forms consist of any one of BID encoding, DPD encoding, Hexadecimal encoding, Binary encoding, BCD encoding or Octal encoding.

4. The system according to claim 1 , wherein the computer architecture is the IBM® z/Architecture, and wherein the machine instruction has a format according to the IBM® z/Architecture.

5. The system according to claim 1 , wherein the machine instruction is in a format of one architecture and is emulated to execute on a processor having another architecture, said another architecture being different from said one architecture.

6. A computer system for executing a machine instruction in a central processing unit, the machine instruction being defined for computer execution according to a computer architecture, the system comprising:
an instruction fetching unit for fetching instructions to be executed;
a floating point arithmetic unit for executing floating point operations of fetched floating point instructions; and
an operand storage in communication with said floating point arithmetic unit;
wherein the computer system performs a method comprising:
a) executing, by a computer processor, a decimal floating point instruction configured to perform a decimal floating point operation, the decimal floating point instruction configured to utilize a round-for-reround mode, the executing comprising:
producing, by the computer processor, an intermediate result of the executed decimal floating point operation, the intermediate result having a high order portion and a low order portion, the high order portion corresponding to a hardware format, the hardware format having a first number of digits of precision including a least significant digit;
rounding, by an Arithmetic Unit (AU), the high order portion according to the round-for-reround mode, wherein:
based on a least significant digit of the high order portion being 0 or 5 and based on the value of the low order portion being greater than 0, storing a tag field entry in a tag store comprising a plurality of tag field entries, the tag field entry indicating an inexact result;
based on the least significant digit of the high order portion of the intermediate result produced not being 0 or 5, or based on the value of the low order portion of said intermediate result produced being 0, storing a tag field entry in a tag store comprising a plurality of tag field entries, the tag field entry indicating an exact result; and

storing, in a computer processor storage unit, the high order portion as a final result of the executed decimal floating point operation in a store related to the tag field; and

b) subsequent to execution of the decimal floating point instruction, executing, by the processor, a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to any of a plurality of rounding precisions, the executing the decimal reround instruction execution comprising:
fetching, by the computer processor, the stored final result of the executed decimal floating point operation, the fetched final result having a first number of bits representing a first number of decimal digits;
fetching, by the computer processor, the tag field associated with the fetched result;
determining, by the computer processor, a decimal reround instruction specified rounding precision of the plurality of rounding precisions, wherein the specified rounding precision employs a second number of digits consisting of a number of digits less than or equal to the first number of digits;
based on the fetched tags, rounding, by the AU, the fetched final result to the second number of digits specified by the decimal reround interaction; and
storing, in a computer processor storage unit, the rounded final result of the executed decimal floating point operation as a result of the decimal reround instruction.

7. The system according to claim 6 , wherein rounding further comprises:
based on a value of a most significant digit of a decimal number represented by the low order portion of the intermediate result produced being greater than 4, storing a tag field entry in the tag

Assignees

• IBM

Inventors

• Cowlishaw Michael F
• Smith Sr Ronald M
• Smith Ronald M
• Yeh Phil C

Classifications

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F9/30014

  with variable precision · CPC title

• G06F7/49973

  Rounding towards negative infinity, e.g. truncation of two's complement numbers (G06F7/49957 takes precedence) · CPC title

• G06F7/49915

  Mantissa overflow or underflow in handling floating-point numbers · CPC title

• G06F7/49968

  Rounding towards positive infinity (G06F7/49957 takes precedence) · CPC title