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Round for reround mode in a decimal floating point instruction

US9201846B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9201846-B2
Application numberUS-201313848885-A
CountryUS
Kind codeB2
Filing dateMar 22, 2013
Priority dateMar 1, 2007
Publication dateDec 1, 2015
Grant dateDec 1, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for executing a machine instruction in a central processing unit, the machine instruction being defined for computer execution according to a computer architecture, said method comprising: a) executing, by the computer processor, a decimal floating point instruction configured to perform a decimal floating point operation, the decimal floating point instruction configured to utilize a round-for-reround mode, the executing step comprising: producing…

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Frequently asked questions

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What does patent US9201846B2 cover?
A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 f…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F17/10. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).