Wafer placement correction in indexed multi-station processing chambers

Patent metadata

Field	Value
Publication number	US-12217985-B2
Application number	US-202017593791-A
Country	US
Kind code	B2
Filing date	Mar 27, 2020
Priority date	Mar 29, 2019
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

Systems and techniques for determining and using multiple types of offsets for providing wafers to a transfer pedestal of a multi-station processing chamber are disclosed. Such techniques may be used to provide pedestal-specific offsets that may be selected based on which pedestal of a multi-station chamber is assigned to a particular wafer. Similar techniques may be used to provide wafer support-specific offsets based on which indexer arm of an indexer is assigned to a given wafer.

First claim

What is claimed is:

1. An apparatus comprising:
a first chamber having an indexer and N pedestals in a circular array centered around a rotational axis of the indexer, wherein a pedestal of the N pedestals of the first chamber is a transfer pedestal, each pedestal of the first chamber is configured to support a wafer, N is an integer greater than one, the first chamber includes an active wafer centering system associated with the transfer pedestal, and the first chamber is a multi-station semiconductor processing chamber;
a wafer handling robot having a robot arm configured to provide individual wafers to the transfer pedestal of the first chamber; and
a controller that includes one or more processors and one or more memory devices, wherein:
the one or more processors, the one or more memory devices, the wafer handling robot, the indexer of the first chamber, and the active wafer centering system of the first chamber are operably connected with each other, and
the one or more memory devices store computer-executable instructions for controlling the one or more processors to:
a) select one of the N pedestals of the first chamber as a destination pedestal of the first chamber for a first wafer;
b) select a first pedestal offset associated with the destination pedestal of the first chamber from a set of N pedestal offsets of the first chamber, each pedestal offset of the set of N pedestal offsets of the first chamber associated with a different pedestal of the N pedestals of the first chamber;
c) obtain information from the active wafer centering system of the first chamber indicative of a horizontal location of the center of the first wafer while the first wafer is on the robot arm;
d) determine a first end effector offset associated with the first wafer based, at least in part, on the information obtained from the active wafer centering system of the first chamber indicative of the horizontal location of the center of the first wafer;
e) cause the robot arm to provide the first wafer to the transfer pedestal of the first chamber based on the first pedestal offset and the first end effector offset;
f) the indexer of the first chamber to move the first wafer from the transfer pedestal of the first chamber to the destination pedestal of the first chamber; and
g) the first chamber to perform one or more semiconductor processing operations on the first wafer on the destination pedestal of the first chamber.

2. The apparatus of claim 1 , wherein:
the transfer pedestal of the first chamber is the destination pedestal of the first chamber, and
the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to cause the first chamber to process the first wafer while the first wafer is on the destination pedestal of the first chamber.

3. The apparatus of claim 1 , and the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to:
perform (a) through (e) for each of N wafers, wherein a different pedestal of the N pedestals of the first chamber is selected as the destination pedestal of the first chamber for each of the N wafers;
cause the indexer of the first chamber to move each wafer of the first through M th wafers of the N wafers to the destination pedestal of the first chamber selected for each wafer of the first through M th wafers, wherein M=N−1 and the transfer pedestal of the first chamber is the destination pedestal of the first chamber for the Nth wafer; and
cause the first chamber to perform one or more semiconductor processing operations on the N wafers while each wafer of the N wafers is supported by the corresponding destination pedestal of the first chamber.

4. The apparatus of claim 1 , wherein the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to:
f) select one of the N pedestals of the first chamber as a destination calibration pedestal of the first chamber for a first calibration wafer;
g) obtain information from the active wafer centering system indicative of a horizontal location of the center of the first calibration wafer;
h) cause the robot arm to provide the first calibration wafer to the transfer pedestal of the first chamber;
i) cause the first chamber to perform a calibration process that includes performing one or more semiconductor processing operations on the first calibration wafer; and
j) obtain a preliminary pedestal offset for the destination calibration pedestal of the first chamber based, at least in part, on information indicative of non-uniformity of the first calibration wafer resulting from the performance of the calibration process in (i) and the horizontal location of the center of the first calibration wafer.

5. The apparatus of claim 4 , wherein the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to cause the indexer of the first chamber to move the first calibration wafer from the transfer pedestal of the first chamber to the destination calibration pedestal of the first chamber in between the performance of (h) and (i).

6. The apparatus of claim 4 , wherein the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to use the preliminary pedestal offset as the pedestal offset for the destination calibration pedestal of the first chamber.

7. The apparatus of claim 4 , wherein the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to:
k) obtain information from the active wafer centering system associated with the transfer pedestal of the first chamber indicative of a horizontal location of the center of a second calibration wafer;
l) Cause the robot arm to provide the second calibration wafer to the transfer pedestal of the first chamber;
m) cause the first chamber to perform the calibration process on the second calibration wafer; and
n) determine the pedestal offset for the destination calibration pedestal based at least in part on information indicative of non-uniformity of the second calibration wafer, the information indicative of non-uniformity of the first calibration wafer, the horizontal location of the center of the first calibration wafer, and the horizontal location of the center of the second calibration wafer.

8. The apparatus of claim 1 , wherein one of the N pedestals of the first chamber is a secondary transfer pedestal, the first chamber includes a secondary active wafer centering system associated with the secondary transfer pedestal, the wafer handling robot has an additional robot arm configured to provide individual wafers to the secondary transfer pedestal of the first chamber; and
the one or more memory devices store additional computer-executable instructions for further controlling the one or more processors to:
f) select one of the N pedestals of the first chamber as a destination pedestal of the first chamber for an additional wafer;
g) select a corresponding pedestal offset associated with the destination pedestal of the first chamber from N second pedestal offsets of the first chamber, each pedestal offset of the first chamber associated with a different pedestal of the N pedestals of the first chamber;
h) obtain information from the secondary active wafer centering system of the first chamber indicative of a horizontal location of the center of the additional wafer;
i) determine a second end effector offset associated with the additional wafer based, at least in part, on the information obtained from the secondary

Assignees

• Lam Res Corp

Inventors

• Topping Stephen
• Niu Dong

Classifications

• H10P72/7621

  characterised by supporting two or more semiconductor substrates · CPC title

• H10P72/7618

  characterised by a movable susceptor, stage or support, others than those only rotating on their own vertical axis, e.g. susceptors on a rotating carrousel · CPC title

• H10P72/7614

  characterised by a plurality of individual support members, e.g. support posts or protrusions · CPC title

• H10P72/3302

  Mechanical parts of transfer devices · CPC title

• H10P72/0464 Primary

  characterised by the construction of the transfer chamber · CPC title