Manufacturing method of semiconductor structure with epitaxial layer forming extension portion

Patent metadata

Field	Value
Publication number	US-12213305-B2
Application number	US-202117455054-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Apr 15, 2021
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor structure, comprising:
providing a base, wherein the base comprises multiple active regions;
forming multiple spaced bit line structures on the base, wherein the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures;
forming a first conductive layer in the trench, wherein a void is formed in the first conductive layer;
removing a part of the first conductive layer located in the trench, such that the remaining first conductive layer forms a conductive structure, wherein the conductive structure and the bit line structures enclose a first groove, and the bottom of the first groove exposes the void;
forming an epitaxial layer on an inner wall of the first groove; and
allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void;
forming a filling layer in the first groove, such that the filling layer fills the first groove and covers the top surfaces of the bit line structures;
forming multiple spaced etch grooves in the filling layer, wherein an extension direction of the etch grooves is perpendicular to the first direction;
removing the filling layer and the conductive structure exposed in the etch grooves, such that the remaining conductive structure forms a conductive plug, and a second groove is formed where the filling layer and the conductive structure are removed, wherein the second groove exposes the base;
forming a fourth dielectric layer in the second groove, such that the fourth dielectric layer fills the second groove; and
removing the filling layer, such that the conductive plug and the fourth dielectric layer enclose a third groove.

2. The manufacturing method of a semiconductor structure according to claim 1 , wherein the forming the epitaxial layer on the inner wall of the first groove comprises:
forming the epitaxial layer on the inner wall of the first groove by a low-pressure vapor deposition process, wherein the epitaxial layer covers top surfaces of the bit line structures; and the epitaxial layer and the first conductive layer are made of polysilicon.

3. The manufacturing method of a semiconductor structure according to claim 2 , wherein a thickness of the epitaxial layer is 1-5 nm.

4. The manufacturing method of a semiconductor structure according to claim 3 , wherein the allowing the epitaxial layer to epitaxially grow comprises:
performing the epitaxial growth at 400-600° C. by a reactant gas comprising at least one of SiCl 4 , SiHCl 3 , SiH 4 , or SiH 2 Cl 2 .

5. The manufacturing method of a semiconductor structure according to claim 4 , wherein prior to the forming the epitaxial layer on the inner wall of the first groove, after the removing a part of the first conductive layer located in the trench, the manufacturing method further comprises:
introducing chlorine gas or hydrogen gas into the first groove to pre-treat a top surface of the conductive structure.

6. The manufacturing method of a semiconductor structure according to claim 1 , wherein a depth ratio of the first groove to the trench is 1:5 to 1:3.

7. The manufacturing method of a semiconductor structure according to claim 1 , wherein the forming multiple spaced bit line structures on the base comprises:
forming bit lines on the base, wherein an intermediate trench is formed between adjacent bit lines;
forming isolation sidewalls on side surfaces of the bit lines facing the intermediate trench, wherein the isolation sidewalls each comprise a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence; the first dielectric layer is in contact with a side surface of the intermediate trench; the third dielectric layer covers a bottom wall of the intermediate trench and top surfaces of the bit lines; and the third dielectric layer located in the same intermediate trench encloses the trench.

8. The manufacturing method of a semiconductor structure according to claim 7 , wherein after the forming the isolation sidewalls on the side surfaces of the bit lines facing the intermediate trench, before the step of forming the first conductive layer in the trench, the manufacturing method further comprises:
removing the third dielectric layer located on the bottom wall of the trench, such that the active region is exposed in the trench; and
removing a part of the active region exposed in the trench to form an accommodating recess in the active region, wherein the first conductive layer is filled in the accommodating recess.

9. The manufacturing method of a semiconductor structure according to claim 8 , wherein the removing a part of the active region exposed in the trench to form the accommodating recess in the active region comprises:
removing a part of the active region exposed in the trench by dry etching by an etching gas comprising at least one of SF 6 , NF 3 and Cl 2 , at 5-100 mTorr and 200-1,000 W.

10. The manufacturing method of a semiconductor structure according to claim 9 , wherein after the removing a part of the first conductive layer located in the trench, before the forming the epitaxial layer on the inner wall of the first groove, the manufacturing method further comprises:
removing the third dielectric layer on the top surfaces of the bit lines and a sidewall of the first groove, such that a top surface of the remaining third dielectric layer is flush with that of the conductive structure.

11. The manufacturing method of a semiconductor structure according to claim 8 , wherein the bit lines each comprise a second conductive layer, a barrier layer, a third conductive layer and an insulating layer stacked in sequence.

12. The manufacturing method of a semiconductor structure according to claim 1 , wherein after the removing the filling layer, the manufacturing method further comprises:
forming a pad in the third groove, wherein one end of the pad is connected to the conductive plug, and the other end of the pad is connected to a capacitor.

13. The manufacturing method of a semiconductor structure according to claim 12 , wherein a material of the filling layer comprises silicon oxide.

14. A semiconductor structure, manufactured by a manufacturing method of a semiconductor structure, the method comprising:
providing a base, wherein the base comprises multiple active regions;
forming multiple spaced bit line structures on the base, wherein the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures;
forming a first conductive layer in the trench, wherein a void is formed in the first conductive layer;
removing a part of the first conductive layer located in the trench, such that the remaining first conductive layer forms a conductive structure, wherein the conductive structure and the bit line structures enclose a first groove, and the bottom of the first groove exposes the void;
forming an epitaxial layer on an inner wall of the first groove; and
allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void;
forming a filling layer in the first groove, such that the filling layer fills the first groove and covers the top surfaces of the bit line structures;
forming multiple spaced etch grooves in the filling layer, wherein an extension direction of the etch grooves is perpendicular to the first direction;
removing the filling layer and the conductive structure exposed in the etch grooves, such that the

Assignees

• Changxin Memory Tech Inc

Inventors

• Chen Longyang
• Liu Zhongming
• Bai Shijie
• Yu Yexiao

Classifications

• H10B12/038

  the capacitor being in a trench in the substrate · CPC title

• H10B12/37

  the capacitor being at least partially in a trench in the substrate · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title