Direct swap caching with zero line optimizations

Patent metadata

Field	Value
Publication number	US-11847459-B2
Application number	US-202217718920-A
Country	US
Kind code	B2
Filing date	Apr 12, 2022
Priority date	Apr 12, 2022
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

First claim

What is claimed:

1. A method for managing a system having a near memory and a far memory, the method comprising:
receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory;
analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) a first information related to whether the near memory contains the block of data or whether the far memory contains the block of data and (2) a second information related to whether a data portion associated with the block of data is all zeros; and
in response to determining that the far memory contains the block of data and that a data portion associated with the block of data is all zeros, instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

2. The method of claim 1 , wherein each block of data comprises a cache line for a central processing unit (CPU) associated with the system.

3. The method of claim 1 , wherein the synthesizing the data portion corresponding to the block of data to generate the synthesized data portion comprises a memory controller associated with the near memory providing grounded bits associated with the data portion.

4. The method of claim 2 , further comprising a system level cache controller, associated with the system, tracking information regarding whether a cache line is guaranteed to be located in the near memory.

5. The method of claim 4 , further comprising the system level cache controller tracking information regarding whether a cache line located in the far memory comprises all zeros.

6. The method of claim 2 , wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a size of the second swappable range of memory addresses associated with the far memory is fixed.

7. A system having a near memory and a far memory, the system comprising:
a near memory controller configured to receive a request from a requestor to read a block of data that is either stored in the near memory or the far memory;
the near memory controller further configured to analyze a metadata portion associated with the block of data, the metadata portion comprising: both (1) a first information related to whether the near memory contains the block of data or whether the far memory contains the block of data and (2) a second information related to whether a data portion associated with the block of data is all zeros; and
the near memory controller further configured to, in response to determining that the far memory contains the block of data and that a data portion associated with the block of data is all zeros, instead of retrieving the data portion from the far memory, synthesize the data portion corresponding to the block of data to generate synthesized a data portion and transmit the synthesized data portion to the requestor.

8. The system of claim 7 , wherein the system further comprises a central processing unit (CPU), and wherein each block of data comprises a cache line for the CPU.

9. The system of claim 7 , wherein the near memory controller is configured to provide grounded bits associated with the data portion as the synthesized data portion.

10. The system of claim 8 , further comprising a system level cache controller configured to track information regarding whether a cache line is guaranteed to be located in the near memory.

11. The system of claim 10 , wherein the system level cache controller is further configured to track information regarding whether a cache line located in the far memory comprises all zeros.

12. The system of claim 8 , wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a size of the second swappable range of memory addresses associated with the far memory is fixed.

13. The system of claim 7 , wherein the far memory is managed using a far memory controller configured to communicate with the near memory controller.

14. A method for managing a system having a near memory and a far memory, the method comprising:
receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory;
analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) a first information related to whether the near memory contains the block of data or whether the far memory contains the block of data and (2) a second information related to whether a data portion associated with the block of data is all zeros;
in response to determining that the far memory contains the block of data and that a data portion associated with the block of data is all zeros, instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor; and
performing a speculative swap by writing a data portion corresponding to a block of data previously stored in the near memory to the far memory and updating a metadata portion stored in the near memory to reflect that the near memory contains a data portion corresponding to the block of data previously stored in the far memory.

15. The method of claim 14 , wherein each block of data comprises a cache line for a central processing unit (CPU) associated with the system.

16. The method of claim 14 , wherein the synthesizing the data portion corresponding to the block of data to generate the synthesized data portion comprises a near memory controller associated with the near memory providing grounded bits associated with the data portion.

17. The method of claim 15 , further comprising a system level cache controller, associated with the system, tracking information regarding whether a cache line is guaranteed to be located in the near memory.

18. The method of claim 17 , further comprising the system level cache controller tracking information regarding whether a cache line located in the far memory comprises all zeros.

19. The method of claim 15 , wherein the near memory comprises a first swappable range of memory addresses allocable to a process for execution by the CPU, wherein the far memory comprises a second swappable range of memory addresses allocable to the process for execution by the CPU, and wherein a ratio of a size of the first swappable range of memory addresses associated with the near memory and a size of the second swappable range of memory addresses associated with the far memory is fixed.

20. The method of claim 14 , wherein the near memory is managed using a near memory controller, and wherein the far memory is managed using a far memory controller configured to communicate with the near memory controller.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Agarwal Ishwar
• Chrysos George
• Rosell Martinez Oscar
• Bak Yevgeniy

Classifications

• G06F9/3816 Primary

  Instruction alignment, e.g. cache line crossing · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F9/505

  considering the load · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title