Apparatus and method for endurance of non-volatile memory banks via wear leveling and outlier compensation

Patent metadata

Field	Value
Publication number	US-11670352-B1
Application number	US-202117344820-A
Country	US
Kind code	B1
Filing date	Jun 10, 2021
Priority date	Jun 4, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

First claim

We claim:

1. An apparatus comprising:
a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, wherein an individual memory bit-cell includes a non-volatile material which includes one of: non-linear polar material, a magnet, or a resistive material, wherein an individual memory bank has a plurality of words, and wherein an individual word has a valid bit; and
a memory controller coupled to the memory, wherein the memory controller includes one or more circuitries to improve memory endurance of the memory via wear leveling and outlier compensation, wherein the outlier compensation is according to a value of the valid bit, and wherein the valid bit indicates whether the individual word is reliable.

2. The apparatus of claim 1 , wherein the individual memory bank of the plurality of memory banks includes N cache lines or words and a gap word.

3. The apparatus of claim 2 , wherein the memory controller is to issue a request a write to a first address of the individual memory bank or a read from a second address of the individual memory bank, and wherein the one or more circuitries are to cause a swap of the gap word with an adjacent cache line or word in response to the request.

4. The apparatus of claim 3 , wherein the gap word has a gap pointer, wherein the one or more circuitries is to increment the gap pointer after the swap.

5. The apparatus of claim 1 , wherein the non-linear polar material includes one of: ferroelectric material, paraelectric material, or non-linear dielectric.

6. The apparatus of claim 1 , wherein the wear leveling is with random swap injection.

7. The apparatus of claim 6 comprises a random number generator to generate a random number between a first number and a second number for the random swap injection.

8. The apparatus of claim 7 , wherein the individual memory bank of the plurality of memory banks includes N cache lines or words and a gap word.

9. The apparatus of claim 8 , wherein the memory controller is to issue a request a write to a first address of the individual memory bank or a read from a second address of the individual memory bank, wherein the one or more circuitries are to cause a swap of the gap word with a cache line or word in response to the request and based on the random number being less than a second threshold.

10. The apparatus of claim 9 , wherein the gap word has a gap pointer, wherein the one or more circuitries is to increment the gap pointer after the swap, and wherein the second threshold is substantially 0.5.

11. The apparatus of claim 1 , wherein the memory controller is to improve the memory endurance of the memory according to a value of the valid bit.

12. The apparatus of claim 11 , wherein the memory controller is to read the value of the valid bit for the individual word of the individual memory bank.

13. The apparatus of claim 11 , wherein the memory controller is to lookup a redundant memory for data if the value of the valid bit indicates it is set.

14. The apparatus of claim 13 , wherein the memory controller is to apply an error correction code to the data from the redundant memory or from the individual word if the value of the valid bit indicates it is set.

15. The apparatus of claim 11 , wherein the valid bit is stored in a first SRAM.

16. The apparatus of claim 13 , wherein the redundant memory comprises a second SRAM.

17. A method to improve memory endurance of a memory via wear leveling, the method comprising:
requesting a write to an address of an individual memory bank or a read to the address of the individual memory bank, wherein the individual memory bank is part of a plurality of memory banks comprising memory bit cells, wherein an individual memory bit-cell includes a capacitor comprising non-linear polar material, wherein requesting the write or the read includes a reference to the individual memory bank, and wherein the individual memory bank of the plurality of memory banks includes N cache lines or words and a gap word;
incrementing a number of references by one upon requesting the write or the read;
comparing the number of references with a threshold;
swapping the gap word with an adjacent cache line or word in response to the number of references is equal to the threshold;
requesting a read to an address of the individual memory bank;
reading a value of a valid bit for a cache line or word from among the N cache lines or words, in response to requesting the read;
looking up a redundant memory for data if the value of the valid bit indicates it is set; and
applying an error correction code to the data from the redundant memory or data from the word or from the cache line or word if the value of the valid bit indicates it is set.

18. The method of claim 17 , wherein the valid bit is stored in a first SRAM, and wherein the redundant memory comprises a second SRAM.

19. A system comprising:
a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, wherein an individual memory bit-cell includes a non-volatile material includes one of: non-linear polar material, a magnet, or a resistive material, wherein an individual memory bank has a plurality of words, and wherein an individual word has a valid bit;
a processor circuitry coupled to the memory;
a memory controller coupled to the memory, wherein the memory controller includes one or more circuitries to improve memory endurance of the memory via wear leveling and outlier compensation, wherein the outlier compensation is according to a value of the valid bit, and wherein the valid bit indicates whether the individual word is reliable; and
a communication interface to allow the processor circuitry to communicate with another device.

20. The system of claim 19 , wherein the memory controller is to:
read the value of the valid bit for the individual word of the individual memory bank;
lookup a redundant memory for data if the value of the valid bit indicates it is set; and
apply an error correction code to the data from the redundant memory or from the individual word if the value of the valid bit indicates it is set, wherein the valid bit is stored in a first SRAM, and wherein the redundant memory comprises a second SRAM.

Assignees

• Kepler Computing Inc

Inventors

• Wilkerson Christopher B
• Manipatruni Sasikanth
• Dokania Rajeev Kumar
• Mathuriya Amrita

Classifications

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G11C11/2295

  Protection circuits or methods · CPC title