Chip-to-chip optical coupling for photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-12204155-B2
Application number	US-202217850828-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Sep 24, 2021
Publication date	Jan 21, 2025
Grant date	Jan 21, 2025

Abstract

A photonic integrated circuit including multiple elements formed by different processes onto separate chips can be manufactured by defining, via photolithography processes for example, complementary geometries onto each separate chip. Thereafter, the complementary geometries can be aligned and engaged, thereby optically and mechanically intercoupling the several chips to define a single photonic integrated circuit.

First claim

What is claimed is:

1. A photonic integrated circuit comprising:
a first chip defining a first surface and comprising:
a first surface feature extending from the first surface and having a first triangular cross-sectional profile extending along a first direction and defining a first conductive surface;
a second surface feature extending from the first surface and having a second triangular cross-sectional profile extending along a second direction different from the first direction and defining a second conductive surface; and
a first photonic circuit element disposed on the first chip and defining an optical axis; and

a second chip defining a second surface and comprising:
a third surface feature defined into the second surface and engaged with the first surface feature;
a first conductive layer disposed over the third surface feature and conductively coupled to the first conductive surface;
a fourth surface feature defined into the second surface and engaged with the second surface feature;
a second conductive layer disposed over the fourth surface feature and conductively coupled to the second conductive surface; and
a second photonic circuit element disposed on the second chip, aligned with the optical axis, and optically coupled to the first photonic circuit element.

2. The photonic integrated circuit of claim 1 , wherein the first chip and the second chip are formed from silicon.

3. The photonic integrated circuit of claim 1 , wherein:
the third surface feature has a third triangular cross-sectional profile smaller than the first triangular cross-sectional profile.

4. The photonic integrated circuit of claim 1 , wherein the third surface feature has a rectilinear cross-sectional profile oriented along the first direction.

5. The photonic integrated circuit of claim 1 , wherein the first photonic circuit element comprises a laser light emitting element.

6. The photonic integrated circuit of claim 5 , wherein the second photonic circuit element comprises a waveguide.

7. A method of manufacturing a photonic integrated circuit, the method comprising:
forming a first channel having a first triangular cross-sectional profile into a first chip comprising a first photonic circuit element;
forming a second channel into the first chip, the second channel having a second triangular cross-sectional profile at a perpendicular angle relative to the first triangular cross-sectional profile of the first channel;
disposing a first conductive layer over the first channel;
disposing a second conductive layer over the second channel;
forming a first protrusion from a second chip comprising a second photonic circuit element;
forming a second protrusion from the second chip, the second protrusion offset by the angle from the first protrusion;
disposing a third conductive layer over the first protrusion;
disposing a fourth conductive layer over the second protrusion; and
aligning the first photonic circuit element with the second photonic circuit element by aligning the first chip with the second chip such that:
the first protrusion extends into the first channel;
the second protrusion extends into the second channel;
the first conductive layer conductively couples to the third conductive layer; and
the second conductive layer conductively couples to the fourth conductive layer.

8. The method of claim 7 , wherein the first channel is formed, at least in part, by a photolithography process.

9. The method of claim 8 , wherein the second channel is formed, at least in part, by the photolithography process.

10. The method of claim 8 , wherein the photolithography process comprises an anisotropic etch or a directional etch.

11. The method of claim 8 , wherein the first protrusion and the second protrusion are formed, at least in part, by the photolithography process.

12. The method of claim 7 , wherein the first channel and the first protrusion have complementary geometry.

13. The method of claim 7 , wherein the second channel and the second protrusion have complementary geometry.

14. A photonic integrated circuit comprising:
a first chip defining a first surface and comprising:
a first channel defined into the first surface and having a first triangular cross-sectional profile and defining a first conductive surface;
a second channel defined into the first surface and perpendicular to the first channel and having a second triangular cross-sectional profile perpendicular to the first triangular cross-sectional profile and defining a second conductive surface; and
a first photonic circuit element disposed on the first chip; and

a second chip defining a second surface and comprising:
a first protrusion extending from the second surface, engaging the first channel and conductively coupling to the first conductive surface;
a second protrusion extending from the second surface, engaging the second channel and conductively coupling to the second conductive surface;
a second photonic circuit element disposed on the second chip and optically coupled to the first photonic circuit element as a result of engagement between the first and second channels and the first and second protrusions, respectively.

15. The photonic integrated circuit of claim 14 , wherein the first chip is mechanically coupled to the second chip.

Assignees

• Apple Inc

Inventors

• Witmer Jeremy D
• Bismuto Alfredo
• Hill Jeffrey T
• Suh Junkyo
• Yilmaz Yigit O

Classifications

• G02B6/4232

  using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072) · CPC title

• G02B6/423 Primary

  using guiding surfaces for the alignment · CPC title