Structures for bonding a direct-bandgap chip to a silicon photonic device

Patent metadata

Field	Value
Publication number	US-9882073-B2
Application number	US-201414509979-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Oct 9, 2013
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A composite photonic device comprises a platform, a chip, and a contact layer. The platform comprises silicon. The chip is made of a III-V material. The contact layer has indentations to help control a flow of solder during bonding of the platform with the chip. In some embodiments, pedestals are placed under an optical path to prevent solder from flowing between the chip and the platform at the optical path.

First claim

What is claimed is:

1. A photonic device comprising:
a base layer comprising a crystalline material, the base layer having a recess formed therein, wherein a direction that is parallel with a surface of the base layer outside of the recess defines a horizontal direction and a direction that is normal to the surface of the base layer outside of the recess defines a vertical direction;
a device layer, wherein:
the device layer is above the base layer;
the device layer defines an opening bounded on all sides by a plurality of device layer walls such that a portion of the base layer that includes the recess is exposed through the opening in the device layer;
the device layer comprises a first silicon waveguide portion extending along a first portion of an optical path and a second silicon waveguide portion extending along a second portion of the optical path, such that the optical path is defined by a line that begins with the first silicon waveguide portion, continues through the opening in the direction of the first silicon waveguide portion, and continues along the second silicon waveguide portion;
the first silicon waveguide portion has a first termination at a first wall of the plurality of device layer walls at a first side of the opening;
the second silicon waveguide portion has a second termination at a second wall of the plurality of device layer walls at a second side of the opening, across the opening from the first side of the opening; and wherein:

the base layer defines two or more pedestals below the opening, wherein:
a first one of the two or more pedestals extends from a bottommost surface of the recess in a direction normal to the bottommost surface toward the device layer; and
the first pedestal is disposed adjoining the first wall of the plurality of device layer walls directly under the line of the optical path;
a second one of the two or more pedestals extends from the bottommost surface of the recess in the direction normal to the bottommost surface toward the device layer; and
the second pedestal is disposed adjoining the second wall of the plurality of device layer walls directly under the line of the optical path.

2. The photonic device of claim 1 , wherein the base layer defines three or more pedestals.

3. The photonic device of claim 1 , wherein the photonic device further comprises a chip disposed within the opening in the device layer.

4. The photonic device of claim 1 , wherein:
the recess formed in the base layer defines a plurality of base layer walls;
the plurality of base layer walls are, respectively, coplanar with ones of the plurality of device layer walls, such that the plurality of base layer walls bound part of the recess;
the base layer is a handle portion of a silicon-on-insulator (SOI) wafer; and
the device layer is part of the SOI wafer.

5. The photonic device of claim 1 , wherein:
the two or more pedestals are two pedestals,
the photonic device further comprises a third pedestal; and
a bond material is positioned around three sides of the third pedestal and at least partially around a fourth side of the third pedestal.

6. The photonic device of claim 1 , wherein:
a chip comprising a crystalline material is bonded to the base layer of the photonic device;
the first and second pedestals comprise a crystalline material; and
a height of the chip relative to the base layer is set by the crystalline material of the chip resting against flat crystalline material surfaces of the first pedestal and the second pedestal such that there is no material between the flat crystalline material surface of the first pedestal and the chip, or between the flat crystalline material surface of the second pedestal and the chip.

7. The photonic device of claim 6 , wherein:
the chip comprises an active layer; and
the height of the chip relative to the base layer vertically aligns the active layer with the first termination of the first silicon waveguide portion and the second termination of the second silicon waveguide portion.

8. The photonic device of claim 7 , further comprising a first optical bridge between the active layer and the first termination of the first silicon waveguide portion, and a second optical bridge between the active layer and the second termination of the second silicon waveguide portion.

9. The photonic device of claim 3 , wherein:
the bottommost surface of the recess forms a plane that is horizontal and unbroken between the first pedestal and the second pedestal beneath the optical path; and
the photonic device further comprises a contact layer that covers a portion of the bottommost surface of the recess, beneath the optical path.

10. The photonic device of claim 9 , wherein:
the chip comprises:
an active layer, and
a chip contact layer bonded to a bottom side of the chip;

a bond material is placed atop the contact layer between the first pedestal and the second pedestal;
the bond material bonds the contact layer with the chip contact layer; and
the bond material is conductive so as to provide an electrical path for the active layer, the electrical path being continuous along a planar surface that is both horizontal and uninterrupted beneath the optical path between the first pedestal and the second pedestal.

Assignees

• Skorpios Tech Inc

Inventors

• Krasulick Stephen B
• Dallesasse John
• Mizrahi Amit
• Creazzo Timothy
• Marchena Elton
• Spann John Y

Classifications

• H01S5/021 Primary

  Silicon based substrates · CPC title

• H01S5/3013

  AIIIBV compounds · CPC title

• H01S5/026

  Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) · CPC title

• H01S2301/176

  Specific passivation layers on surfaces other than the emission facet · CPC title

• G02B6/12004

  Combinations of two or more optical elements · CPC title