Optimized solder pads for solder induced alignment of opto-electronic chips

Patent metadata

Field	Value
Publication number	US-9543736-B1
Application number	US-201514947621-A
Country	US
Kind code	B1
Filing date	Nov 20, 2015
Priority date	Nov 20, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A technique relates to assembling a multi-chip system. A first chip stack element having two major surfaces and a first solder pad, a first vertical stop, a first lateral stop and a first waveguiding element is provided. A second chip stack element having two major surfaces and including a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element is provided. A solder material is plated to form a plated solder pad. A technique includes pre-aligning the first chip stack element and the second chip stack element, raising the temperature to a temperature above the melting temperature of the solder material, and flowing solder through the flow resistor. Aspects include aligning the first and second waveguiding elements and cooling the connected assembly to re-solidify the solder material.

First claim

What is claimed is:

1. A method of assembling a multi-chip system, comprising:
providing a first chip stack element having two major surfaces, the first chip stack element comprising a first solder pad on a plane of one of the major surfaces, a first vertical stop, a first lateral stop, and a first waveguiding element;
providing a second chip stack element having two major surfaces, the second chip stack element comprising a second solder pad, a flow resistor connected to the second solder pad, a second vertical stop, a second lateral stop, a reservoir pad connected to the flow resistor, and a second waveguiding element;
optionally plating the reservoir pad with a reservoir solder material;
plating a solder material on the second solder pad to form a plated solder pad, wherein the height of the plated solder material on the second solder pad is at a height that is higher than the height of plated reservoir solder material;
pre-aligning the first chip stack element and the second chip stack element to bring the first solder pad in proximity to the plated solder pad;
raising the temperature to a temperature above the melting temperature of the solder material;
flowing solder through the flow resistor;
aligning the first and second waveguiding elements;
cooling the connected assembly to re-solidify the solder material.

2. The method of claim 1 , comprising plating the first solder pad with a first pad solder material, wherein a summed height of the first pad solder material solder and the plated solder material on the second solder pad is such that it prevents physical contact between the vertical stop and the second vertical stop and the summed height is such that the lateral stop and the second lateral stop do not overlap to bring the first solder pad in proximity to the second solder pad when the first and second chip stack elements are pre-aligned.

3. The method of claim 1 , wherein the first and second waveguiding elements are first aligned in the horizontal direction, and then aligned in the vertical direction.

4. The method of claim 1 , the method further comprising plating reservoir solder material on the reservoir pads prior to pre-aligning.

5. The method of claim 1 , comprising plating a first solder pad with solder material prior to pre-aligning.

6. The method of claim 1 , wherein the second chip element is an indium phosphide or gallium arsenide chip.

7. The method of claim 1 , wherein the solder is AgSn or AuSn.

8. The method of claim 1 , wherein the solder pad and plated solder pad are offset after cooling the connected assembly.

9. The method of claim 1 , wherein the second chip stack element comprises a thermal sink.

10. The method of claim 1 , wherein the waveguide in first chip stack element is a III-V laser waveguide or III-V semiconductor optical amplifier waveguide.

11. A multi-chip system, comprising
a first chip stack element having two major surfaces, the first chip stack element comprising a first solder pad on a plane of one of the major surfaces, a first vertical stop, a first lateral stop, and a first waveguiding element;
a second chip stack element having two major surfaces, the second chip stack element comprising a second solder pad, a flow resistor connected to the solder pad, a reservoir pad connected to the flow resistor, a second waveguiding element, a second vertical stop, and a second lateral stop; and
a solder material connecting the first solder pad to the second solder pad;
wherein the first lateral stop is in proximity to the second lateral stop;
wherein the first vertical is in proximity to the second vertical stop;
wherein the first waveguiding element is in proximity to the second waveguiding element; and
wherein the solder pad and plated solder pad are offset in the horizontal direction.

12. The multi-chip system of claim 11 , wherein the flow resistor and the reservoir pad are covered with solder material.

13. The multi-chip system of claim 12 , wherein the height of the solder material on the flow resistor and reservoir pad is smaller than the height of the solder material connecting the first solder pad of the first chip stack element to the second solder pad of the second chip stack element.

14. The multi-chip system of claim 11 , wherein the first vertical stop is in contact with the second vertical stop.

15. The multi-chip system of claim 11 , wherein the first lateral stop is in contact with the second lateral stop.

16. The multi-chip system of claim 11 , further comprising a polymeric underfill adjacent to the first or second waveguiding element.

17. The multi-chip system of claim 11 , wherein the second chip element is an indium phosphide or gallium arsenide chip.

18. The multi-chip system of claim 11 , wherein the solder material is AgSn or AuSn.

19. A chip stack element, comprising
a first major surface,
a second major surface,
a waveguiding element,
a solder pad,
solder plated on the solder pad to form a plated solder pad,
a flow resistor connected to the plated solder pad, and
a reservoir pad connected to the flow resistor; and
a reservoir solder plated on the reservoir pad, wherein the solder plated on the solder pad is plated at a height that is lower than the height of the reservoir solder.

Assignees

• IBM

Inventors

• Barwicz Tymon
• Martin Yves

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H01S5/02284

  Electricity · mapped topic

• H01S5/3013

  AIIIBV compounds · CPC title

• H01S5/02469

  Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC · CPC title

• G02B6/13

  Integrated optical circuits characterised by the manufacturing method · CPC title