Gate line plug structures for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12199167-B2
Application number	US-202117216550-A
Country	US
Kind code	B2
Filing date	Mar 29, 2021
Priority date	Nov 30, 2017
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a gate line over a substrate, the gate line having a first side and a second side, wherein the gate line has a discontinuity;
a dielectric plug in the discontinuity of the gate line, the dielectric plug comprising a dielectric material liner, and the dielectric plug comprising a dielectric material fill laterally surrounded by the dielectric material liner;
a first dielectric spacer adjacent the first side of the gate line, the first dielectric spacer continuous along the first side of the gate line and the dielectric plug;
a second dielectric spacer adjacent the second side of the gate line, the second dielectric spacer continuous along the second side of the gate line and the dielectric plug, wherein one of the first dielectric spacer or the second dielectric spacer has a first lateral width at a horizontal level at a first location adjacent to the dielectric plug and has a second lateral width at the horizontal level at a second location adjacent to the dielectric plug, the second lateral width different than the first lateral width;
a first trench contact laterally adjacent the first dielectric spacer, the first trench contact continuous along the first side of the gate line and the dielectric plug; and
a second trench contact laterally adjacent the second dielectric spacer, the second trench contact continuous along the second side of the gate line and the dielectric plug.

2. The integrated circuit structure of claim 1 , wherein the dielectric material liner comprises silicon and nitrogen.

3. The integrated circuit structure of claim 1 , wherein the dielectric material fill comprises silicon and oxygen.

4. The integrated circuit structure of claim 1 , wherein the dielectric material liner comprises silicon and nitrogen, and wherein the dielectric material fill comprises silicon and oxygen.

5. An integrated circuit structure, comprising:
a first gate electrode over a first fin, the first gate electrode having a first long side and a second long side between a first short end and a second short end;
a second gate electrode over a second fin, the second gate electrode having a first long side and a second long side between a first short end and a second short end;
a dielectric plug between the second short end of the first gate electrode and the first short end of the second gate electrode, the dielectric plug comprising a first dielectric material, and the dielectric plug comprising a second dielectric material laterally surrounded by the first dielectric material;
a first dielectric spacer continuous along the first long side of the first gate electrode, along the dielectric plug, and along the first long side of the second gate electrode;
a second dielectric spacer continuous along the second long side of the first gate electrode, along the dielectric plug, and along the second long side of the second gate electrode, wherein one of the first dielectric spacer or the second dielectric spacer has a first lateral width at a horizontal level at a first location adjacent to the dielectric plug and has a second lateral width at the horizontal level at a second location adjacent to the dielectric plug, the second lateral width different than the first lateral width;
a first trench contact laterally adjacent the first dielectric spacer, the first trench contact continuous along the first long side of the first gate electrode, along the dielectric plug, and along the first long side of the second gate electrode; and
a second trench contact laterally adjacent the second dielectric spacer, the second trench contact continuous along the second long side of the first gate electrode, along the dielectric plug, and along the second long side of the second gate electrode.

6. The integrated circuit structure of claim 5 , further comprising:
a first source or drain region in the first fin proximate the first long side of the first gate electrode;
a second source or drain region in the second fin proximate the first long side of the second gate electrode, wherein the first trench contact is on the first source or drain region and on the second source or drain region;
a third source or drain region in the first fin proximate the second long side of the first gate electrode; and
a fourth source or drain region in the second fin proximate the second long side of the second gate electrode, wherein the second trench contact is on the third source or drain region and on the fourth source or drain region.

7. The integrated circuit structure of claim 5 , wherein the first dielectric material comprises silicon and nitrogen.

8. The integrated circuit structure of claim 5 , wherein the second dielectric material comprises silicon and oxygen.

9. The integrated circuit structure of claim 5 , wherein the first dielectric material comprises silicon and nitrogen, and wherein the second dielectric material comprises silicon and oxygen.

10. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a gate line over a substrate, the gate line having a first side and a second side, wherein the gate line has a discontinuity;
a dielectric plug in the discontinuity of the gate line, the dielectric plug comprising a dielectric material liner, and the dielectric plug comprising a dielectric material fill laterally surrounded by the dielectric material liner;
a first dielectric spacer adjacent the first side of the gate line, the first dielectric spacer continuous along the first side of the gate line and the dielectric plug;
a second dielectric spacer adjacent the second side of the gate line, the second dielectric spacer continuous along the second side of the gate line and the dielectric plug, wherein one of the first dielectric spacer or the second dielectric spacer has a first lateral width at a horizontal level at a first location adjacent to the dielectric plug and has a second lateral width at the horizontal level at a second location adjacent to the dielectric plug, the second lateral width different than the first lateral width;
a first trench contact laterally adjacent the first dielectric spacer, the first trench contact continuous along the first side of the gate line and the dielectric plug; and
a second trench contact laterally adjacent the second dielectric spacer, the second trench contact continuous along the second side of the gate line and the dielectric plug.

11. The computing device of claim 10 , further comprising:
a memory coupled to the board.

12. The computing device of claim 10 , further comprising:
a communication chip coupled to the board.

13. The computing device of claim 10 , further comprising:
a camera coupled to the board.

14. The computing device of claim 10 , further comprising:
a battery coupled to the board.

15. The computing device of claim 10 , further comprising:
an antenna coupled to the board.

16. The computing device of claim 10 , wherein the component is a packaged integrated circuit die.

17. The computing device of claim 10 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

18. The computing device of claim 10 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

19. The computing device of claim 10 , wherein the dielectric material

Assignees

• Intel Corp

Inventors

• Ho Byron
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title