Semiconductor device including a structure for higher integration

Patent metadata

Field	Value
Publication number	US-12199123-B2
Application number	US-202318354792-A
Country	US
Kind code	B2
Filing date	Jul 19, 2023
Priority date	Oct 5, 2018
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

There is provided a semiconductor device which includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate is provided with a first electrode including a first protruding portion and a first base portion. The first protruding portion includes a first abutting surface. The first base portion is linked to the first protruding portion and has volume greater than volume of the first protruding portion. The second semiconductor substrate is provided with a second electrode including a second protruding portion and a second base portion. The second protruding portion includes a second abutting surface that abuts the first abutting surface. The second base portion is linked to the second protruding portion and has volume greater than volume of the second protruding portion. The second semiconductor substrate is stacked on the first semiconductor substrate.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first semiconductor substrate that includes a first metal portion including a first protruding portion and a first base portion, wherein
the first protruding portion includes a first abutting surface,
the first base portion is linked to the first protruding portion, and
an area corresponding to the first base portion is greater than an area corresponding to the first protruding portion in a plane orthogonal to a stack direction of the first semiconductor substrate and a second semiconductor substrate;

a first barrier layer that surrounds the first protruding portion and the first base portion in a plane parallel to the stack direction of the first semiconductor substrate and the second semiconductor substrate;
the second semiconductor substrate that includes a second metal portion including a second protruding portion and a second base portion, wherein
the second protruding portion includes a second abutting surface that abuts the first abutting surface,
the second base portion is linked to the second protruding portion, and
the second semiconductor substrate is stacked on the first semiconductor substrate; and

a second barrier layer that surrounds the second protruding portion and the second base portion in the plane parallel to the stack direction of the first semiconductor substrate and the second semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein an area corresponding to the second base portion is greater than an area corresponding to the second protruding portion in the plane orthogonal to the stack direction of the first semiconductor substrate and the second semiconductor substrate.

3. The semiconductor device according to claim 1 , wherein the first abutting surface and the second abutting surface form abutting sections that are joined together based on plasma junction.

4. The semiconductor device according to claim 1 , wherein a volume of the first base portion is greater than a volume of the first protruding portion.

5. The semiconductor device according to claim 1 , further comprising:
a first insulating film that covers a part of a surface of the first base portion; and
a second insulating film that covers at least a part of a surface of the second base portion.

6. A semiconductor device, comprising:
a first substrate that includes a first metal portion including a first protruding portion and a first base portion, wherein
the first protruding portion includes a first abutting surface, and
the first base portion is linked to the first protruding portion;

a first insulating layer, wherein at least a part of the first metal portion is embedded in the first insulating layer;
a first barrier layer that surrounds the first protruding portion and the first base portion in a plane parallel to a stack direction of the first substrate and a second substrate;
the second substrate that has a second metal portion including a second protruding portion and a second base portion, wherein
the second protruding portion includes a second abutting surface that abuts the first abutting surface,
the second base portion is linked to the second protruding portion, and
the second substrate is stacked on the first substrate;

a second insulating layer, wherein at least a part of the second metal portion is embedded in the second insulating layer;
a second barrier layer that surrounds the second protruding portion and the second base portion in the plane parallel to the stack direction of the first substrate and the second substrate; and
an insulating film that covers at least a part of a surface of the first base portion.

7. The semiconductor device according to claim 6 , wherein an area corresponding to the first base portion is greater than an area corresponding to the first protruding portion in a plane orthogonal to the stack direction of the first substrate and the second substrate.

8. The semiconductor device according to claim 6 , wherein an area corresponding to the second base portion is greater than an area corresponding to the second protruding portion in a plane orthogonal to the stack direction of the first substrate and the second substrate.

9. The semiconductor device according to claim 6 , wherein the first abutting surface and the second abutting surface form abutting sections that are joined together based on plasma junction.

10. The semiconductor device according to claim 6 , wherein a volume of the first base portion is greater than a volume of the first protruding portion.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Hagimoto Yoshiya
• Fujii Nobutoshi

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/732

  having shape changed during the connecting · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title