Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-2016343763-A1
Application number	US-201615228894-A
Country	US
Kind code	A1
Filing date	Aug 4, 2016
Priority date	Jul 5, 2011
Publication date	Nov 24, 2016
Grant date	—

Abstract

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

First claim

What is claimed is:

1 . A solid-state imaging device comprising:
a first semiconductor substrate including a pixel array and a first multilayer wiring layer having a first connecting interconnect embedded in a first insulating layer, and a second semiconductor substrate including a logic circuit and a second multilayer wiring layer having a second connecting interconnect embedded in a second insulating layer, wherein the first semiconductor substrate and the second semiconductor substrate are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another and are electrically connected via the first connecting interconnect and the second connecting interconnect to one another, wherein an insulating thin film is sandwiched between a bonding face of the first substrate and a bonding face of the second substrate, and wherein the first insulating layer and the second insulating layer are formed from SiO2.

2 . The solid-state imaging device of claim 1 , wherein the bonding face of the first semiconductor substrate includes a surface of the first connecting interconnect and a surface of the first insulating layer.

3 . The solid-state imaging device of claim 2 , wherein the bonding face of the second semiconductor substrate includes a surface of the second connecting interconnect and a surface of the second insulating layer.

4 . The solid-state imaging device of claim 1 , wherein the pixel array includes a plurality of photoelectric conversion portions.

5 . The solid-state imaging device of claim 4 , further comprising:
a plurality of first electrodes, and a plurality of second electrodes, wherein one first electrode and one second electrode are provided for each photoelectric conversion portion in the plurality of photoelectric conversion portions.

6 . The solid-state imaging device of claim 5 , wherein each photoelectric conversion portion in the plurality of photoelectric conversion portions is connected to a wiring line in the first multilayer wiring layer.

7 . The solid-state imaging device of claim 6 , wherein a protection film is formed on a first face side of the first semiconductor substrate.

8 . The solid-state imaging device of claim 7 , wherein a color filter layer is disposed on the protection film.

9 . The solid-state imaging device of claim 8 , wherein on-chip lenses are disposed on the color filter layer.

10 . The solid-state imaging device of claim 1 , wherein the first connecting interconnect is formed from Cu.

11 . The solid-state imaging device of claim 10 , wherein the second connecting interconnect is formed from Cu.

12 . A solid-state imaging device comprising:
a first semiconductor substrate including a pixel array and a first multilayer wiring layer having a first connecting interconnect embedded in a first insulating layer, and a second semiconductor substrate including a logic circuit and a second multilayer wiring layer having a second connecting interconnect embedded in a second insulating layer, wherein the first semiconductor substrate and the second semiconductor substrate are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another and are electrically connected via the first connecting interconnect and the second connecting interconnect to one another, wherein an insulating thin film is sandwiched between a bonding face of the first substrate and a bonding face of the second substrate, and wherein the insulating thin film is formed from one of SiN, SiCN, SiON SiC and an organic resin material.

13 . The solid-state imaging device of claim 12 , wherein the first insulating layer and the second insulating layer are formed from SiO2.

14 . The solid-state imaging device of claim 12 , wherein the bonding face of the first semiconductor substrate includes a surface of the first connecting interconnect and a surface of the first insulating layer.

15 . The solid-state imaging device of claim 14 , wherein the bonding face of the second semiconductor substrate includes a surface of the second connecting interconnect and a surface of the second insulating layer.

16 . The solid-state imaging device of claim 12 , wherein the pixel array includes a plurality of photoelectric conversion portions.

17 . The solid-state imaging device of claim 16 , further comprising:
a plurality of first electrodes, and
a plurality of second electrodes, wherein one first electrode and one second electrode are provided for each photoelectric conversion portion in the plurality of photoelectric conversion portions.

18 . The solid-state imaging device of claim 17 , wherein each photoelectric conversion portion in the plurality of photoelectric conversion portions is connected to a wiring line in the first multilayer wiring layer.

19 . The solid-state imaging device of claim 18 , wherein a protection film is formed on a first face side of the first semiconductor substrate.

20 . The solid-state imaging device of claim 12 , wherein the first connecting interconnect is formed from Cu.

Assignees

• Sony Corp

Inventors

• Kagawa Yoshihisa
• Aoyagi Kenichi
• Hagimoto Yoshiya
• Fujii Nobutoshi

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/721

  having structure or size changed during the connecting · CPC title

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/334

  Thermocompression bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title