Method of fabricating multi-substrate semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016141282-A1
Application number	US-201514940621-A
Country	US
Kind code	A1
Filing date	Nov 13, 2015
Priority date	Nov 13, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a first opening in a first insulating interlayer on a first substrate; forming a first barrier layer in the first opening and on portions of the first insulating interlayer adjacent the first opening; forming a first conductive layer on the first barrier layer; chemical mechanical polishing the first conductive layer and the first barrier layer to expose a top surface of the first insulating interlayer and form a first conductive pattern structure having a first barrier layer pattern and a first conductive pattern on the first barrier layer pattern, the first conductive pattern having a top surface higher than a top surface of a portion of the first barrier layer pattern on a sidewall of the first insulating interlayer in the first opening; forming a first bonding insulating layer structure on the first conductive pattern structure and the first insulating interlayer; planarizing the first bonding insulating layer structure to expose a top surface of the first conductive pattern structure; forming a second opening in a second insulating interlayer on a second substrate; forming a second barrier layer in the first opening and on portions of the second insulating interlayer adjacent the second opening; forming a second conductive layer on the second barrier layer; chemical mechanical polishing the second conductive layer and the second barrier layer to expose a top surface of the second insulating interlayer and form a second conductive pattern structure having a second barrier layer pattern and a second conductive pattern on the second barrier layer pattern, the second conductive pattern having a top surface higher than a top surface of a portion of the second barrier layer pattern on a sidewall of the second insulating interlayer in the second opening; forming a second bonding insulating layer structure on the second conductive pattern structure and the second insulating interlayer; planarizing the second bonding insulating layer structure to expose a top surface of the second conductive pattern structure; and bonding the first and second substrates together with the first and second conductive pattern structures in contact with each other.

2 . The method of claim 1 , wherein chemical mechanical polishing the first conductive layer and the first barrier layer leaves the top surface of the first barrier layer on the side wall of the first opening substantially coplanar with the top surface of the first insulating interlayer, and wherein chemical mechanical polishing the second conductive layer and the second barrier layer leaves the top surface of the second barrier layer on the side wall of the second opening substantially coplanar with the top surface of the second insulating interlayer.

3 . The method of claim 1 , wherein chemical mechanical polishing the first conductive layer and the first barrier layer leaves the top surface of the first barrier layer on the side wall of the first opening lower than the top surface of the first insulating interlayer, and wherein chemical mechanical polishing the second conductive layer and the second barrier layer leaves the top surface of the second barrier layer on the side wall of the second opening lower than the top surface of the second insulating interlayer.

4 . The method of claim 1 , further comprising forming a third insulating interlayer between the first substrate and the first insulating interlayer, the third insulating interlayer containing a third conductive pattern structure therein,
and wherein the first opening exposes a top surface of the third conductive pattern structure.

5 . The method of claim 4 , further comprising forming a first etch stop layer between the third insulating interlayer and the first insulating interlayer, the first etch stop layer including silicon nitride, silicon carbonitride, silicon carbide, and/or silicon oxynitride,
and wherein forming the first opening comprises removing portions of the first insulating interlayer and the first etch stop layer to expose the top surface of the third conductive pattern structure.

6 . The method of claim 1 , further comprising performing a plasma treatment on at least one of the first and second substrates having the first and second conductive pattern structures thereon prior to bonding the first and second substrates together.

7 . The method of claim 6 , wherein the plasma treatment uses a nitrogen plasma, an oxygen plasma, a hydrogen plasma, a mixed plasma including nitrogen and hydrogen, a tetrafluoromethane (CF 4 ) plasma, and/or an ammonia plasma.

8 . The method of claim 1 , wherein planarizing the first bonding insulating layer structure to expose a top surface of the first conductive pattern structure comprises chemical mechanical polishing the first bonding insulating layer structure, and wherein planarizing the second bonding insulating layer structure to expose a top surface of the second conductive pattern structure comprises chemical mechanical polishing the second bonding insulating layer structure.

9 . The method of claim 1 , wherein the first bonding insulating layer structure comprises at least two bonding insulating layers comprising different materials and wherein the second bonding insulating layer structure comprises at least two bonding insulating layers comprising different materials.

10 . The method of claim 9 , wherein at least one of the bonding insulating layers in each of the first and second bonding insulating layer structures comprises silicon carbonitride and wherein at least one of the bonding insulating layers in each of the first and second bonding insulating layer structures comprises silicon nitride.

11 . A method of manufacturing a semiconductor device, the method comprising:
forming a third insulating interlayer on a first substrate, the third insulating interlayer containing a third conductive pattern structure therein; sequentially forming a first etch stop layer and a first insulating interlayer on the third insulating interlayer to cover the third conductive pattern structure; forming a first opening through the first insulating interlayer and the first etch stop layer to expose a top surface of the third conductive pattern structure; forming a first barrier layer on the exposed top surface of the third conductive pattern structure, a sidewall of the first opening, and the first insulating interlayer; forming a first conductive layer on the first barrier layer to fill a remaining portion of the first opening; performing a CMP process on the first conductive layer and the first barrier layer until a top surface of the first insulating interlayer is exposed to form a first conductive pattern structure having a first barrier layer pattern and a first conductive pattern, the first conductive pattern having a top surface higher than a top surface of the first barrier layer pattern; forming a first bonding insulating layer structure on the first conductive pattern structure and the first insulating interlayer; planarizing the first bonding insulating layer structure until a top surface of the first conductive pattern structure is exposed; forming a fourth insulating interlayer on a second substrate, the fourth insulating interlayer containing a fourth conductive pattern structure therein; sequentially forming a second etch stop layer and a second insulating interlayer on the fourth insulating interlayer to cover the fourth conductive pattern structure; forming a second opening through the second insulating interlayer and the second etch stop layer to expose a top surface of the fourth conductive patte

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Joo-Hee
• Kang Pil-Kyu
• Kim Seok-Ho
• Kim Tae-Yeong
• Kim Hyo-Ju
• Park Byung-Lyul
• Park Jum-Yong
• An Jin-Ho
• Lee Kyu-Ha
• Hong Yi-Koan

Classifications

• H10W80/701

  characterised by the pads after the direct bonding · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/102

  Controlling the environment during the bonding, e.g. the temperature or pressure · CPC title

• H10W80/016

  Cleaning · CPC title