Fin doping and integrated circuit structures resulting therefrom

Patent metadata

Field	Value
Publication number	US-12199098-B2
Application number	US-202117211745-A
Country	US
Kind code	B2
Filing date	Mar 24, 2021
Priority date	Mar 24, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Fin doping, and integrated circuit structures resulting therefrom, are described. In an example, an integrated circuit structure includes a semiconductor fin. A lower portion of the semiconductor fin includes a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm 3 . A gate stack is over and conformal with an upper portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a semiconductor fin, wherein a lower portion of the semiconductor fin comprises a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm 3 ;
a gate stack over and conformal with an upper portion of the semiconductor fin;
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

2. The integrated circuit structure of claim 1 , wherein the N-type dopants comprise phosphorous dopant atoms, and the P-type dopants comprise boron dopant atoms.

3. The integrated circuit structure of claim 1 , wherein the N-type dopants comprise arsenic dopant atoms, and the P-type dopants comprise boron dopant atoms.

4. The integrated circuit structure of claim 1 , wherein the region further comprises carbon dopant atoms.

5. The integrated circuit structure of claim 1 , wherein the semiconductor fin protrudes from a monocrystalline silicon substrate, and the semiconductor fin is a silicon fin.

6. The integrated circuit structure of claim 1 , wherein the first and second source or drain regions are embedded source or drain regions.

7. An integrated circuit structure, comprising:
a semiconductor fin, wherein a lower portion of the semiconductor fin comprises a region having both N-type dopants and P-type dopants with a net excess of the N-type dopants of at least 2E18 atoms/cm 3 ;
a gate stack over and conformal with an upper portion of the semiconductor fin;
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

8. The integrated circuit structure of claim 7 , wherein the N-type dopants comprise phosphorous dopant atoms, and the P-type dopants comprise boron dopant atoms.

9. The integrated circuit structure of claim 7 , wherein the N-type dopants comprise arsenic dopant atoms, and the P-type dopants comprise boron dopant atoms.

10. The integrated circuit structure of claim 7 , wherein the region further comprises carbon dopant atoms.

11. The integrated circuit structure of claim 7 , wherein the semiconductor fin protrudes from a monocrystalline silicon substrate, and the semiconductor fin is a silicon fin.

12. The integrated circuit structure of claim 7 , wherein the first and second source or drain regions are embedded source or drain regions.

13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin, wherein a lower portion of the semiconductor fin comprises a region having both N-type dopants and P-type dopants with a net excess of the P-type dopants of at least 2E18 atoms/cm 3 ;
a gate stack over and conformal with an upper portion of the semiconductor fin;
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

14. The computing device of claim 13 , further comprising:
a memory coupled to the board.

15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.

16. The computing device of claim 13 , further comprising:
a camera coupled to the board.

17. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.

18. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin, wherein a lower portion of the semiconductor fin comprises a region having both N-type dopants and P-type dopants with a net excess of the N-type dopants of at least 2E18 atoms/cm 3 ;

a gate stack over and conformal with an upper portion of the semiconductor fin;
a first source or drain region at a first side of the gate stack; and
a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

19. The computing device of claim 18 , further comprising:
a memory coupled to the board.

20. The computing device of claim 18 , further comprising:
a communication chip coupled to the board.

21. The computing device of claim 18 , further comprising:
a camera coupled to the board.

22. The computing device of claim 18 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Weber Cory
• Cea Stephen M
• Pipes Leonard C
• Hwangbo Seahee
• Mehandru Rishabh
• Keys Patrick
• Yaung Jack
• Ou Tzu-Min

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title