FinFET structures having silicon germanium and silicon fins with suppressed dopant diffusion

Patent metadata

Field	Value
Publication number	US-9837415-B2
Application number	US-201514750455-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A finned structure is fabricated using a bulk silicon substrate having a carbon-doped epitaxial silicon germanium layer. A pFET region of the structure includes fins having silicon germanium top portions and an epitaxial carbon-doped silicon germanium diffusion barrier that suppresses dopant diffusion from the underlying n-well into the silicon germanium fin region during device fabrication. The structure further includes an nFET region including silicon fins formed from the substrate. The carbon-doped silicon germanium diffusion barrier has the same or higher germanium content than the silicon germanium fins.

First claim

What is claimed is:

1. A method comprising:
obtaining a first structure comprising a crystalline silicon substrate having an nFET region and a pFET region, a p-well region within the nFET region of the substrate and an n-well region within the pFET region of the substrate;
forming a recess within the pFET region of the crystalline silicon substrate down to the n-well region;
epitaxially growing a carbon-doped silicon germanium layer in the recess on the n-well region;
epitaxially growing an essentially undoped silicon germanium layer in the recess on the carbon-doped silicon germanium layer, the carbon-doped silicon germanium layer having a higher percentage of germanium than is contained in the silicon germanium layer, the carbon-doped silicon germanium layer being positioned between the n-well and the silicon germanium layer;
forming a plurality of parallel first fins from the block structure and the n-well region, each first fin comprising a silicon germanium portion from the silicon germanium layer, a carbon-doped silicon germanium portion from the carbon-doped silicon germanium layer, and an n-doped portion from part of the n-well region in the pFET region, and
forming a plurality of parallel second fins comprising a silicon portion from the crystalline silicon substrate and a p-doped portion from the p-well region in the nFET region.

2. The method of claim 1 , wherein the n-well region of the substrate is doped with arsenic.

3. The method of claim 2 , further including the step of depositing a dielectric layer on the substrate and in areas between the first fins and second fins, thereby obtaining a second structure.

4. The method of claim 3 , wherein the carbon-doped silicon germanium portions of the first fins include exposed portions extending above the dielectric layer.

5. The method of claim 3 , wherein the step of growing the carbon-doped silicon germanium layer on the n-well region further includes in situ doping the carbon-doped silicon germanium layer with arsenic using an arsenic precursor and reducing the concentration of the arsenic precursor during the growth of the carbon-doped silicon germanium layer until completely removed, thereby creating an in situ doped graded SiGe:C(As) layer.

6. The method of claim 5 , wherein the carbon-doped silicon germanium portions of the first fins include exposed portions that extend above the dielectric layer.

7. The method of claim 3 , further including the step of thermally processing the second structure, wherein the carbon-doped silicon germanium portions of the first fins suppresses arsenic diffusion into the silicon germanium portions of the first fins.

8. The method of claim 7 , further including the step of forming p-type FinFET devices in the pFET region using the first fins.

9. The method of claim 8 , further including the step of forming n-type FinFET devices in the nFET region using the second fins.

10. The method of claim 1 , wherein the steps of growing the carbon-doped silicon germanium layer and the silicon germanium layer cause the carbon-doped silicon germanium layer to have a one to five percent higher percentage of germanium than is contained in the silicon germanium layer.

11. The method of claim 10 , wherein the step of growing the carbon-doped silicon germanium layer further includes causing the carbon-doped silicon germanium layer to have a composition of Si 1−x Ge x :C where x is at least 0.2 and an atomic carbon concentration of at least 1×10 19 cm −3 .

12. The method of claim 1 , wherein the step of growing the carbon-doped silicon germanium layer further includes causing the carbon-doped silicon germanium layer to have a composition of Si 1−x Ge x :C where x is at least 0.2.

13. The method of claim 12 , wherein the step of growing the carbon-doped silicon germanium layer further includes causing the carbon-doped silicon germanium layer to have an atomic carbon concentration of at least 1×10 19 cm −3 .

14. The method of claim 13 , wherein the n-well region of the substrate is doped with arsenic.

15. The method of claim 1 , wherein the carbon-doped silicon layer has an atomic carbon concentration of between 1×10 19 cm −3 and 2×10 20 cm −3 .

16. The method of claim 15 , wherein the carbon-doped silicon germanium layer has a one to five percent greater percentage of germanium than the silicon germanium layer.

17. The method of claim 16 , further including adding arsenic in situ in decreasing concentration during the epitaxial growth of the carbon-doped silicon germanium layer until addition of the arsenic is completely discontinued.

18. A method comprising:
obtaining a first structure comprising a crystalline silicon substrate having an nFET region and a pFET region, a p-well region within the nFET region of the substrate and an n-well region within the pFET region of the substrate;
forming a recess within the pFET region of the crystalline silicon substrate down to the n-well region;
epitaxially growing a carbon-doped silicon germanium layer in the recess on the n-well region while adding arsenic in situ in decreasing concentration during the epitaxial growth of the carbon-doped silicon germanium layer until addition of the arsenic is completely discontinued;
epitaxially growing an essentially undoped silicon germanium layer in the recess on the carbon-doped silicon germanium layer, the carbon-doped silicon germanium layer having the same or greater percentage of germanium as the silicon germanium layer, the carbon-doped silicon germanium layer being positioned between the n-well region and the silicon germanium layer;
forming a plurality of parallel first fins from the n-well region, the carbon-doped silicon germanium layer and the silicon germanium layer, each first fin comprising a silicon germanium portion from the silicon germanium layer, a carbon-doped silicon germanium portion from the carbon-doped silicon germanium layer, and an n-doped portion from part of the n-well region in the pFET region;
forming a plurality of parallel second fins comprising a silicon portion from the crystalline silicon substrate and a p-doped portion from the p-well region in the nFET region;
forming p-type FinFET devices in the pFET region using the first fins;
forming n-type FinFET devices in the nFET region using the second fins;
filling areas between the first fins and the second fins with a dielectric layer such that the carbon-doped silicon germanium portions of the first fins include exposed portions that extend partially above the dielectric layer.

19. The method of claim 18 , wherein the carbon-doped silicon germanium layer has a greater percentage of germanium than the silicon germanium layer.

20. The method of claim 19 , wherein the carbon-doped silicon layer has an atomic carbon concentration of between 1×10 19 cm −3 and 2×10 20 cm −3 .

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L27/0928

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L21/823892

  Electricity · mapped topic