Fracturable data path in a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-12190084-B2
Application number	US-202318099218-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Jan 20, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A coarse-grained reconfigurable (CGR) processor includes a configurable unit comprising a fracturable data path with a plurality of sub-paths. The fracturable data path includes multiple stages that each include an arithmetic logic unit (ALU), selection logic to select two or more inputs for the ALU, and sub-path pipeline registers. The fracturable data path also includes a first output configurable to provide first data selected from any one of the sub-path pipeline registers and a second output configurable to provide second data selected from any one of the sub-path pipeline registers. The configurable unit includes a configuration store to store configuration data to provide a two or more immediate data fields for each stage of the fracturable data path and configuration information for the ALUs, the selection logic, and to select the first data and the second data for the first output and the second output.

First claim

The invention claimed is:

1. A coarse-grained reconfigurable (CGR) processor comprising:
an array of configurable units including a first configurable unit, the first configurable unit comprising a multi-port memory having a first address input associated with a first access port of the multi-port memory and a second address input associated with a second access port of the multi-port memory, and a fracturable data path with a plurality of sub-paths configurable to generate addresses for the multi-port memory:
the fracturable data path comprising:
a plurality of stages, including an initial stage, one or more intermediate stages, and a final stage, each stage of the plurality of stages respectively including an arithmetic logic unit (ALU), selection logic to select two or more inputs for the ALU, and sub-path pipeline registers;
a first output, coupled to a first address input of the multi-port memory, configurable to provide first data selected from any one of the sub-path pipeline registers; and
a second output, coupled to a second address input of the multi-port memory configurable to provide second data, different from the first data, selected from any one of the sub-path pipeline registers;

the first configurable unit further comprising a configuration store to store configuration data including first immediate data, second immediate data, selection information for the selection logic, and ALU configuration information respectively for each stage of the plurality of stages, and output selection information to select the first data and the second data for the first output and the second output, respectively.

2. The CGR processor of claim 1 , the fracturable data path of the first configurable unit including a first set of sub-path input registers;
the selection logic in the one or more intermediate stages and the final stage adapted to select from at least outputs of the sub-path pipeline registers of an immediately preceding stage, outputs of the first set of sub-path input registers, the first immediate data, and the second immediate data associated with that stage and provided by the configuration store; and
the selection logic in the initial stage adapted to select from the outputs of the first set of sub-path input registers, the first immediate data, and the second immediate data associated with the initial stage and provided by the configuration store.

3. The CGR processor of claim 2 , further comprising input multiplexers having outputs respectively coupled to inputs of the first set of sub-path input registers, each of the input multiplexers selecting, for its respective sub-path input register, between:
a first input coupled to a scalar bus of the array of configurable units;
a second input coupled to a lane of a vector bus of the array of configurable units; and
a third input coupled to a counter of the first configurable unit.

4. The CGR processor of claim 3 , wherein the first output is also configurable to provide the first data selected from the outputs of the first set of sub-path input registers.

5. The CGR processor of claim 2 , the fracturable data path of the first configurable unit including a second set of sub-path input registers associated with a second calculation, the first set of sub-path input registers associated with a first calculation;
the selection logic of a stage of the plurality of stages adapted to allow selection between the first set of sub-path input registers and the second set of sub-path input registers based on whether the stage is associated with the first calculation or the second calculation.

6. The CGR processor of claim 2 , each stage of the plurality of stages respectively further including:
bypass logic configurable to select a first sub-path pipeline register to receive an output of the ALU as its input, and to select a second sub-path pipeline register to receive an output of a corresponding sub-path pipeline register of an immediately preceding stage or a corresponding sub-path input register of the first set of sub-path input registers.

7. The CGR processor of claim 1 , wherein the ALUs of the plurality of stages each have a first input, a second input, and a third input, and can perform at least one three-operand operation.

8. The CGR processor of claim 7 , the selection logic of a stage of the plurality of stages configurable to provide the first immediate data to the first input of the ALU of the stage and the second immediate data to the second input of the ALU of the stage.

9. The CGR processor of claim 1 , the first configurable unit further comprising the multi-port memory.

10. The CGR processor of claim 9 , the fracturable data path further comprising:
a third output configurable to provide third data selected from any one of the sub-path pipeline registers;
a fourth output configurable to provide fourth data selected from any one of the sub-path pipeline registers; and
the multi-port memory further comprising:
a third address input, coupled to the third output of the fracturable data path, associated with a third access port of the multi-port memory; and
a fourth address input, coupled to the fourth output of the fracturable data path, associated with a fourth access port of the multi-port memory;
wherein the first access port and the second access port of the multi-port memory are write ports and the third access port and the fourth access port of the multi-port memory are read ports; and
the configuration store is adapted to provide configuration data to select the third data and the fourth data for the third output and the fourth output, respectively.

11. The CGR processor of claim 1 , the configuration store adapted to provide the configuration data to a first set of contiguous stages of the plurality of stages, the first set of contiguous stages including a first starting stage and a first ending stage;
wherein configuration data configures the selection logic of the first starting stage to avoid selecting an output of the sub-path pipeline registers of an immediately preceding stage as any input of the two or more inputs to the ALU of the first starting stage, and to configure the first output to provide data from one of the sub-path pipeline registers of the first ending stage as the first data.

12. The CGR processor of claim 11 , the configuration store adapted to provide the configuration data to a second set of contiguous stages of the plurality of stages, the second set of contiguous stages adjacent to and disjoint from the first set of contiguous stages, the second set of contiguous stages including a second starting stage immediately following the first ending stage and a second ending stage;
wherein configuration data configures the selection logic of the second starting stage to not select an output of the sub-path pipeline registers of the first ending stage as any input of the two or more inputs to the ALU of the second starting stage, and to configure the second output to provide data from one of the sub-path pipeline registers of the second ending stage as the second data.

13. The CGR processor of claim 11 , wherein the first starting stage and the first ending stage are the same stage of the plurality of stages.

14. A non-transitory machine-readable medium comprising configuration information that, in response to being loaded into a configuration store of a first configurable unit in an array of configurable units in a coarse-grained reconfigurable (CGR) processor, causes the first configurable unit to:
receive from the configuration store, at each respective stage of a plurality of stages of a fracturable data path in the first

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Jackson David Brian

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F8/441 Primary

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title