Logic device having a compressed configuration image stored on an internal read only memory
US-8990474-B2 · Mar 24, 2015 · US
Coarse-grained reconfigurable processor and code decompression method thereof
US9348792B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9348792-B2 |
| Application number | US-201313892603-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 13, 2013 |
| Priority date | May 11, 2012 |
| Publication date | May 24, 2016 |
| Grant date | May 24, 2016 |
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Abstract
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A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.
First claim
Opening claim text (preview).
What is claimed is: 1. A coarse-grained reconfigurable processor comprising: a configuration memory configured to store reconfiguration information comprising a header including a compression mode indicator and a compressed code for each of a plurality of units corresponding to a functional unit, a register file, and a multiplexer that are included in each of a plurality of processing elements (PEs), and a body storing uncompressed codes; a decompressor configured to identify an…
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- G06F15/7867Primary
Physics · mapped topic
Electricity · mapped topic
Cross-Sectional Technologies · mapped topic
Cross-Sectional Technologies · mapped topic
- G06F9/06Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9348792B2 cover?
- A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F15/7867. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 24 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).