Selective blocking dielectric formation in a three-dimensional memory structure
US-2016172370-A1 · Jun 16, 2016 · US
US12185540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12185540-B2 |
| Application number | US-202117523447-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 10, 2021 |
| Priority date | Apr 29, 2021 |
| Publication date | Dec 31, 2024 |
| Grant date | Dec 31, 2024 |
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A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
Opening claim text (preview).
The invention claimed is: 1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers; a memory opening extending through the alternating stack; and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film, wherein each of the electrically conductive layers comprises: a metallic fill material layer comprising a metal; a lower metallic liner comprising a first portion of a metallic liner material and contacting a bottom surface of the metallic fill material layer; and an upper metallic liner comprising a second portion of the metallic liner material and contacting a top surface of the metallic fill material layer, wherein the metallic fill material layer, the lower metallic liner, and the upper metallic liner are more distal than the insulating layers from a vertical axis passing through a geometrical center of the memory opening fill structure; wherein each of the electrically conductive layers further comprises a first tubular metal structure in contact with a cylindrical sidewall of the upper metallic liner, in contact with a cylindrical sidewall of the lower metallic liner, and in contact with the metallic fill material layer; and wherein an interface between the first tubular metal structure and the metallic fill material layer comprises: a first cylindrical interface segment having a top periphery that coincides with a bottom periphery of the upper metallic liner; a second cylindrical interface segment having a bottom periphery that coincides with a top periphery of the lower metallic liner; an upper tapered interface segment adjoined to a bottom end of the first cylindrical interface segment; and a lower tapered interface segment adjoined to a top end of the second cylindrical interface segment and adjoined to the upper tapered interface segment. 2. The three-dimensional memory device of claim 1 , wherein the metallic fill material layer contains a seam, and the upper tapered interface segment and the lower tapered interface segment are adjoined to an edge of the seam.
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
characterised by the boundary region between the core and peripheral circuit regions · CPC title
characterised by the boundary region between the core region and the peripheral circuit region · CPC title
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