Method of making ultrahigh density vertical NAND memory device

Patent metadata

Field	Value
Publication number	US-9230976-B2
Application number	US-201414587368-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Jun 30, 2010
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

First claim

What is claimed is:

1. A method of making a monolithic three dimensional NAND string, comprising:
providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material over a sidewall of the at least one opening, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening;
selectively removing the second material layers without removing the first material layers from the stack; and
forming control gates between the first material layers.

2. The method of claim 1 , further comprising forming a blocking dielectric between the first material layers and a side wall of the charge storage material exposed between the first material layers.

3. The method of claim 2 , further comprising forming a cut area on a back side of stack.

4. The method of claim 3 , wherein:
the second material layers are selectively removed through the cut area;
the blocking dielectric is formed through the cut area such that the blocking dielectric contacts the sidewall of the charge storage material exposed between the first material layers; and
the control gates are formed through the cut area.

5. The method of claim 4 , wherein portions of the blocking dielectric between the first material layers have a clam shape, and wherein each of the control gates is located at least partially in an opening in a respective clam-shaped portion of the blocking dielectric.

6. The method of claim 1 , wherein the tunnel dielectric has a straight sidewall and a uniform thickness.

7. The method of claim 1 , wherein the charge storage material comprises a charge storage dielectric material.

8. The method of claim 1 , wherein the charge storage material comprises a floating gate material.

9. The method of claim 8 , wherein the floating gate material comprises polysilicon, metal, metal alloy or metal silicide.

10. The method of claim 1 , wherein the charge storage material comprises conductive nanoparticles.

11. The method of claim 1 , wherein one of the first material layers and the second material layers comprise an oxide and the other of the first material layers and the second material layers comprise a nitride.

12. The method of claim 1 , wherein the semiconductor channel in the at least one opening completely fills the at least one opening with a semiconductor channel material.

13. The method of claim 1 , wherein the semiconductor channel in the at least one opening forms a semiconductor channel material on the side wall of the at least one opening but not in a central part of the at least one opening such that the semiconductor channel material does not completely fill the at least one opening.

14. The method of claim 13 , further comprising forming an insulating fill material in the central part of the at least one opening to completely fill the at least one opening.

15. The method of claim 1 , furthering comprising forming an upper electrode over the semiconductor channel and forming a lower electrode below the semiconductor channel.

16. The method of claim 1 , wherein the control gates comprise conductive or semiconductor control gate material.

17. The method of claim 16 , wherein the control gates comprise tungsten, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or alloys thereof.

18. The method of claim 17 , wherein the control gates comprise tungsten.

19. The method of claim 1 , wherein the step of providing the stack comprises:
etching the stack to form the at least one opening in the stack;
forming the charge storage material over a sidewall of the at least one opening;
forming the tunnel dielectric on the charge storage material in the at least one opening; and
forming the semiconductor channel on the tunnel dielectric in the at least one opening.

20. The method of claim 1 , wherein:
the semiconductor channel extends substantially perpendicular to a major surface of the substrate;
the NAND string comprises a plurality of device levels over the substrate;
the NAND string is vertically oriented, such that at least one memory cell is located over another memory cell in the NAND string; and
each of the plurality of device levels comprises a respective control gate, a respective blocking dielectric portion adjacent to the respective control gate, a respective charge storage material portion adjacent to respective blocking dielectric portion, a respective tunnel dielectric portion adjacent to the respective charge storage material portion, and a respective portion of the semiconductor channel.

Assignees

• Sandisk Technologies Inc

Inventors

• Alsmeier Johann

Classifications

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title