RFFE LNA topology supporting both noncontiguous intraband carrier aggregation and interband carrier aggregation

Patent metadata

Field	Value
Publication number	US-12184248-B2
Application number	US-202217741130-A
Country	US
Kind code	B2
Filing date	May 10, 2022
Priority date	Feb 19, 2019
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

First claim

What is claimed:

1. A method for selectively amplifying a plurality of input signals in a low noise amplifier (LNA) circuit, including:
(a) receiving a first input signal at an input of a first LNA and selectively providing an amplified first output signal to a first circuit output;
(b) receiving a second input signal at an input of a second LNA and selectively providing an amplified second output signal to a second circuit output; and
(c) receiving a third input signal in a split LNA and selectively providing an amplified third output signal to the first circuit output and/or an amplified fourth output signal to the second circuit output.

2. The method of claim 1 , further including:
(a) in a first mode, setting the first LNA to an ON state, and the second LNA and the split LNA to an OFF state;
(b) in a second mode, setting the second LNA to an ON state, and the first LNA and the split LNA to an OFF state;
(c) in a third mode, setting the first LNA to an ON state, the second LNA to an ON state, and the split LNA to an OFF state; and
(d) in a fourth mode, setting the split LNA to an ON state, and the first LNA and the second LNA to an OFF state.

3. The method of claim 1 , further including coupling at least one input matching element to the input of a respective one of the first LNA, the second LNA, and/or the split LNA.

4. The method of claim 1 , further including coupling at least one output load matching element to a respective one of the first circuit output and/or the second circuit output.

5. The method of claim 1 , further including coupling at least one shunt switch between a known potential and the input of a respective one of the first LNA, the second LNA, and/or the split LNA.

6. The method of claim 1 , further including filtering at least one of the first input signal, the second input signal, and/or the third input signal to match a respective amplifier characteristic of the respective first LNA, second LNA, and/or split LNA.

7. The method of claim 1 , further including configuring at least one of the first LNA and the second LNA to include a cascode amplifier stage.

8. The method of claim 1 , further including:
(a) configuring the split LNA to including a first cascode amplifier stage and a second cascode amplifier stage, each cascode amplifier stage having an input configured to receive the third input signal;
(b) configuring the first cascode amplifier stage to selectively provide the amplified third output signal to the first circuit output; and
(c) configuring the second cascode amplifier stage to selectively provide the amplified fourth output signal to the second circuit output.

9. The method of claim 8 , further including coupling a first degeneration element to respective degeneration ports of the first LNA and the first cascode amplifier stage of the split LNA, and a second degeneration element coupled to respective ports outputs of the second LNA and the second cascode amplifier stage of the split LNA.

10. The method of claim 8 , further including configuring the first cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a first node, and configuring the second cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a second node.

11. The method of claim 8 , further including:
(a) configuring the first cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a first node;
(b) configuring the second cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a second node; and
(c) coupling a component between the first node of the first cascode amplifier stage and the second node of the second cascode amplifier stage, wherein the component comprises at least one of a capacitor, a resistor, a capacitor and resistor coupled in series, or a capacitor and resistor coupled in parallel.

12. A method for selectively amplifying a plurality of input signals in a low noise amplifier (LNA) circuit, including:
(a) receiving a first input signal at an input of a first LNA and selectively providing an amplified first output signal to a first circuit output;
(b) receiving a second input signal at an input of a second LNA and selectively providing an amplified second output signal to a second circuit output; and
(c) receiving a third input signal in a split LNA and selectively providing an amplified third output signal to the first circuit output and/or an amplified fourth output signal to the second circuit output;
(d) configuring the split LNA to including a first cascode amplifier stage and a second cascode amplifier stage, each cascode amplifier stage having an input configured to receive the third input signal;
(e) configuring the first cascode amplifier stage to selectively provide an amplified third output signal to the first circuit output; and
(f) configuring the second cascode amplifier stage to selectively provide an amplified fourth output signal to the second circuit output.

13. The method of claim 12 , wherein:
(a) in a first mode, setting the first LNA to an ON state, and the second LNA and the split LNA to an OFF state;
(b) in a second mode, setting the second LNA to an ON state, and the first LNA and the split LNA to an OFF state;
(c) in a third mode, setting the first LNA to an ON state, the second LNA to an ON state, and the split LNA to an OFF state; and
(d) in a fourth mode, setting the split LNA to an ON state, and the first LNA and the second LNA to an OFF state.

14. The method of claim 12 , further including coupling at least one input matching element to the input of a respective one of the first LNA, the second LNA, and/or the split LNA.

15. The method of claim 12 , further including coupling at least one output load matching element to a respective one of the first circuit output and/or the second circuit output.

16. The method of claim 12 , further including coupling at least one shunt switch between a known potential and the input of a respective one of the first LNA, the second LNA, and/or the split LNA.

17. The method of claim 12 , further including filtering at least one of the first input signal, the second input signal, and/or the third input signal to match a respective amplifier characteristic of the respective first LNA, second LNA, and/or split LNA.

18. The method of claim 12 , further including configuring at least one of the first LNA and the second LNA to include a cascode amplifier stage.

19. The method of claim 12 , further including coupling a first degeneration element to respective degeneration ports of the first LNA and the first cascode amplifier stage of the split LNA, and a second degeneration element coupled to respective ports outputs of the second LNA and the second cascode amplifier stage of the split LNA.

20. The method of claim 12 , further including configuring the first cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a first node, and configuring the second cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a second node.

21. The method of claim 20 , further including:
(a) configuring the first cascode amplifier stage to include at least one input transistor series coupled to at least one output transistor at a first node;
(b) configuri

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles
• Yerramilli Phanindra

Classifications

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F3/16

  with field-effect devices · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/45188

  Non-folded cascode stages · CPC title