RFFE LNA topology supporting both noncontiguous intraband carrier aggregation and interband carrier aggregation

Patent metadata

Field	Value
Publication number	US-11336243-B2
Application number	US-202017010311-A
Country	US
Kind code	B2
Filing date	Sep 2, 2020
Priority date	Feb 19, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

First claim

What is claimed:

1. A low noise amplifier (LNA) circuit including:
(a) a first LNA having an input configured to receive a first input signal and configured to selectively provide an amplified first output signal to a first circuit output;
(b) a second LNA having an input configured to receive a second input signal and configured to selectively provide an amplified second output signal to a second circuit output; and
(c) a split LNA having an input configured to receive a third input signal and configured to selectively provide an amplified third output signal to the first circuit output and/or an amplified fourth output signal to the second circuit output.

2. The invention of claim 1 , wherein:
(a) in a first mode, the first LNA is set to an ON state, and the second LNA and the split LNA are set to an OFF state;
(b) in a second mode, the second LNA is set to an ON state, and the first LNA and the split LNA are set to an OFF state;
(c) in a third mode, the first LNA is set to an ON state, the second LNA is set to an ON state, and the split LNA is set to an OFF state; and
(d) in a fourth mode, the split LNA is set to an ON state, and the first LNA and the second LNA are set to an OFF state.

3. The invention of claim 2 , wherein the third input signal is an intraband non-contiguous carrier aggregation radio frequency signal.

4. The invention of claim 2 , wherein in the third mode, the first and second input signals are each an interband carrier aggregation radio frequency signal.

5. The invention of claim 1 , further including at least one input matching element, each coupled to the input of a respective LNA.

6. The invention of claim 1 , further including at least one output load matching element, each coupled to a respective one of the first circuit output or the second circuit output.

7. The invention of claim 1 , further including at least one shunt switch, each coupled between ground and the input of a respective LNA.

8. The invention of claim 1 , wherein at least one of the first input signal, the second input signal, and/or the third input signal is filtered to match an amplifier characteristic of the respective first LNA, second LNA, or split LNA.

9. The invention of claim 1 , wherein at least one of the first LNA and the second LNA comprises a cascode amplifier stage.

10. The invention of claim 1 , wherein the split LNA comprises a first cascode amplifier stage and a second cascode amplifier stage, each cascode amplifier stage having an input configured to receive the third input signal, the first cascode amplifier stage configured to selectively provide the amplified third output signal to the first circuit output and the second cascode amplifier stage configured to selectively provide the amplified fourth output signal to the second circuit output.

11. The invention of claim 10 , further including a first degeneration element coupled to respective degeneration outputs of the first LNA and the first cascode amplifier stage of the split LNA, and a second degeneration element coupled to respective degeneration outputs of the second LNA and the second cascode amplifier stage of the split LNA.

12. The invention of claim 10 , wherein the first and second cascode amplifier stages each comprise at least one input transistor series coupled to at least one output transistor at a node.

13. The invention of claim 11 , further including a component coupled between the respective nodes of the first cascode amplifier stage and the second cascode amplifier stage, wherein the component comprises at least one of a capacitor, a resistor, a series capacitor and resistor, or a parallel capacitor and resistor.

14. The invention of claim 1 ,
(a) wherein the first LNA and the second LNA each comprise a cascode amplifier stage including at least one input transistor series coupled to at least one output transistor at a respective node;
(b) wherein the split LNA comprises a first cascode amplifier stage and a second cascode amplifier stage, each cascode amplifier stage including at least one input transistor series coupled to at least one output transistor at a respective node, each cascode amplifier stage having an input configured to receive the third input signal, the first cascode amplifier stage configured to selectively provide the amplified third output signal from an output of the first cascode amplifier stage to the first circuit output and the second cascode amplifier stage configured to selectively provide the amplified fourth output signal from an output of the second cascode amplifier stage to the second circuit output; and
(c) further including:
(1) a first switch coupled between the node of the cascode amplifier stage of the first LNA and the node of the first cascode amplifier stage of the split LNA;
(2) a second switch coupled between the node of the cascode amplifier stage of the second LNA and the node of the second cascode amplifier stage of the split LNA;
(3) a third switch coupled between the first circuit output and the output of the first cascode amplifier stage of the split LNA; and
(4) a fourth switch coupled between the second circuit output and the output of the second cascode amplifier stage of the split LNA.

15. The invention of claim 1 ,
(a) wherein the first LNA and the second LNA each comprise a cascode amplifier stage including at least one input transistor series coupled to at least one output transistor at a respective node; and
(b) wherein the split LNA comprises a first amplifier stage and a second amplifier stage, the first amplifier stage including at least one input transistor having a drain coupled to the node of the first LNA in a cascode arrangement, and the second cascode amplifier stage including at least one input transistor having a drain coupled to the node of the second LNA in a cascode arrangement.

16. A low noise amplifier (LNA) circuit including:
(a) a first LNA having an input configured to receive a first input signal and configured to selectively provide an amplified first output signal on a first circuit output;
(b) a second LNA having an input configured to receive a second input signal and configured to selectively provide an amplified second output signal on a second circuit output; and
(c) a split LNA comprising a first cascode amplifier stage and a second cascode amplifier stage, each cascode amplifier stage having an input configured to receive a third input signal, the first cascode amplifier stage configured to selectively provide an amplified third output signal from an output of the first cascode amplifier stage to the first circuit output and the second cascode amplifier stage configured to selectively provide an amplified fourth output signal from an output of the second cascode amplifier stage to the second circuit output.

17. The invention of claim 16 , wherein:
(a) in a first mode, the first LNA is set to an ON state, and the second LNA and the split LNA are set to an OFF state;
(b) in a second mode, the second LNA is set to an ON state, and the first LNA and the split LNA are set to an OFF state;
(c) in a third mode, the first LNA is set to an ON state, the second LNA is set to an ON state, and the split LNA is set to an OFF state; and
(d) in a fourth mode, the split LNA is set to an ON state, and the first LNA and the second LNA are set to an OFF state.

18. The invention of claim 17 , wherein the third input signal is an intraband non-contiguous carrier aggregation radio frequency signal.

19. The invention of claim 17 , wherein in the third mode, the first

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles
• Yerramilli Phanindra

Classifications

• H04B1/1638

  Special circuits to enhance selectivity of receivers not otherwise provided for (resonant circuits H03H) · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H04B1/1036 Primary

  with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters (H04B1/123 takes precedence; filter circuits H03H) · CPC title

• H03F3/3089 Primary

  comprising field-effect transistors in the control circuit · CPC title