Drain switched split amplifier with capacitor switching for noise figure and isolation improvement in split mode

Patent metadata

Field	Value
Publication number	US-10686409-B2
Application number	US-201815991980-A
Country	US
Kind code	B2
Filing date	May 29, 2018
Priority date	May 29, 2018
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

First claim

What is claimed is:

1. An amplifier circuit configuration comprising:
(a) a plurality of amplifiers, each including an input transistor and a cascode output transistor;
(b) at least two amp control inputs, each coupled to the cascode output transistor of a corresponding one of the amplifiers; and
(c) at least one switchable drain coupling coupled between drains of input transistors connecting drain terminals of the input transistors of at least two of the amplifiers during the second mode of operation and disconnecting the drain terminals during the first mode of operation;
(d) at least one source switch connecting source terminals of the input transistors of at least two of the amplifiers during a first mode of operation and disconnecting the source terminals during at least a second mode of operation.

2. The amplifier circuit configuration of claim 1 , wherein the drain coupling includes at least an impedance in series with a switch.

3. The amplifier circuit configuration of claim 1 , further comprising an amplifier controller coupled to the amp control inputs, to the at least one source switch and to the switchable drain coupling.

4. The amplifier circuit configuration of claim 1 , wherein the drain coupling includes at least a coupling capacitor coupled in series with a switch.

5. The amplifier circuit configuration of claim 2 , wherein the impedance is established by a resonant circuit.

6. The amplifier circuit configuration of claim 1 , further comprising at least a first switched impedance circuit (SIC), the first SIC having a first and second terminal, the first terminal coupled to the gate of an associated one of the input transistors and the second terminal coupled to the source of the associated input transistor.

7. The amplifier circuit configuration of claim 6 , further comprising at least one additional SIC, each additional SIC having a first and second terminal, the first terminal coupled to the gate of an associated one of the input transistors and the second terminal coupled to the source of the associated input transistor.

8. The amplifier circuit configuration of claim 6 , further comprising an amplifier controller having at least one switch control output, wherein each SIC has a switch control input to which a corresponding switch control output is coupled, the amplifier controller further has at least a first and second amplifier control signal output coupled to corresponding ones of the at least two amp control inputs and having at least a drain coupling control output coupled to the drain coupling and a source switch control output coupled to the source switch.

9. The amplifier circuit configuration of claim 6 , wherein at least one of the SICs includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the SIC.

10. The amplifier circuit configuration of claim 1 , further comprising at least one SIC, each SIC a first and second terminal, the first terminal coupled to the gate of an associated one of the input transistors and the second terminal coupled to ground.

11. The amplifier circuit configuration of claim 10 , further comprising an amplifier controller having at least one switch control output, wherein each SIC has a switch control input to which a corresponding switch control output is coupled.

12. The amplifier circuit configuration of claim 10 , wherein each SIC includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the SIC.

13. The amplifier circuit configuration of claim 1 , further comprising:
(a) a degeneration component; and
(b) a degeneration switch coupled in series with the degeneration component, the series combination of the degeneration component and degeneration switch coupled between the source of one of the input transistors and circuit ground.

14. The amplifier circuit configuration of claim 13 , wherein the degeneration component is an inductor.

15. The amplifier circuit configuration of claim 13 , wherein the degeneration switch is open when the source switch is closed and closed when the source switch is open.

16. The amplifier circuit configuration of claim 13 , further comprising at least a second degeneration component and a second degeneration switch.

17. The amplifier circuit configuration of claim 6 , further comprising:
(a) a degeneration component; and
(b) a degeneration switch coupled in series with the degeneration component, the series combination of the degeneration component and degeneration switch coupled between the source of one of the input transistors and ground.

18. The amplifier circuit configuration of claim 17 , further comprising at least a second degeneration inductor and a second degeneration switch,
wherein each SIC includes a gate capacitor and a gate switch coupled in series between the first terminal and the second terminal of the SIC, and
wherein the second degeneration inductor and second degeneration switch are coupled in series between the source of a second input transistor and ground.

19. The amplifier circuit configuration of claim 17 , further comprising a control module having switch control outputs, wherein the degeneration switch has a switch control input to which one of the switch control outputs is coupled and each SIC has a switch control input to which one of the switch control outputs is coupled.

Assignees

• Psemi Corp

Inventors

• Pal Kashish
• Ayranci Emre
• Sanner Miles

Classifications

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H04L27/2647

  Arrangements specific to the receiver only (equalisation H04L27/01) · CPC title

• H03F2200/489

  A coil being added in the source circuit of a common source stage, e.g. as degeneration means · CPC title