Multi-stack semiconductor device with zebra nanosheet structure

Patent metadata

Field	Value
Publication number	US-12183786-B2
Application number	US-202117536939-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Sep 27, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

First claim

What is claimed is:

1. A multi-stack semiconductor device comprising:
a substrate;
a multi-stack transistor formed on the substrate and comprising a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor,
wherein the nanosheet transistor comprises a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers,
wherein the FinFET comprises at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and
wherein each of the lower and upper gate structures comprises:
a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and
a gate metal pattern formed on the gate oxide layer, the gate metal pattern comprising a work-function metal layer and a conductor plug.

2. The multi-stack semiconductor device of claim 1 ,
wherein at least one of the lower and upper gate structures comprises an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

3. The multi-stack semiconductor device of claim 2 ,
wherein the nanosheet layers comprises silicon (Si), and
wherein silicon germanium (SiGe) is formed between the nanosheet layers.

4. The multi-stack semiconductor device of claim 3 ,
wherein each of the lower and upper gate structures comprises the EG oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

5. The multi-stack semiconductor device of claim 4 ,
wherein the gate oxide layer comprises an interfacial layer and a high-κ layer,
wherein the interfacial layer comprises an oxide material, and
wherein the high-κ layer comprises a material with a dielectric constant higher than the oxide material of the interfacial layer.

6. The multi-stack semiconductor device of claim 1 ,
wherein at least one of the lower and upper gate structures comprises an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure,
wherein a thickness of the gate oxide layer ranges 2 nm to 3 nm, and
wherein a thickness of the EG oxide layer ranges 4 nm to 5 nm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Byounghak
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/681

  having a compositional variation, e.g. multilayered · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title