Vertically stacked dual channel nanosheet devices

Patent metadata

Field	Value
Publication number	US-10658462-B2
Application number	US-201916584168-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Nov 2, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a vertical stack of a first nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet having a first germanium content and a precursor SiGe channel material nanosheet having a second germanium content that is less than the first germanium content, and a second nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet having the first germanium content and a Si channel material nanosheet, wherein the vertical stack is present above a semiconductor substrate and beneath a sacrificial gate structure and a dielectric spacer;
recessing each sacrificial SiGe nanosheet of the first and second nanosheet stacks;
removing the sacrificial gate structure and each recessed sacrificial SiGe nanosheet of the first and second nanosheet stacks to suspend each Si channel material nanosheet and each precursor SiGe channel material nanosheet and to provide a gate cavity;
forming a germanium oxide layer in the gate cavity and on physically exposed surfaces of each suspended Si channel material nanosheet and each suspended precursor SiGe channel material nanosheet;
performing a condensation anneal to convert the suspended precursor SiGe channel material nanosheets into suspended SiGe channel material nanosheets having a third germanium content that is greater than the second germanium content, wherein the germanium oxide layer located on the suspended precursor SiGe channel material nanosheets is also converted into a silicon dioxide layer;
removing the germanium oxide layer and the silicon dioxide layer from each suspended Si channel material nanosheet;
forming a gate dielectric material in the gate cavity and on physically exposed surfaces of each suspended Si channel material nanosheet and each suspended SiGe channel material nanosheet; and
forming a work function metal in the gate cavity and on the gate dielectric material.

2. The method of claim 1 , further comprising forming an inner spacer within a gap formed by the recessing of each sacrificial SiGe nanosheet.

3. The method of claim 1 , further comprising thinning the physically exposed surfaces of each suspended Si channel material nanosheet prior to forming the gate dielectric material.

4. The method of claim 3 , wherein the thinning is performed utilizing a series of oxidation and etching steps.

5. The method of claim 4 , wherein the condensation anneal does not convert a portion of the precursor SiGe material nanosheet that is not in direct physically contact with the germanium oxide layer, wherein each non-converted portion of the precursor SiGe material nanosheet provides a SiGe channel extension region.

6. The method of claim 3 , wherein the thinning is performed utilizing a chemical oxide removal (COR) process.

7. The method of claim 1 , further comprising:
forming a pFET S/D region on physically exposed sidewalls of each precursor SiGe channel material nanosheet of the first nanosheet stack;
forming a dielectric material on each pFET S/D region; and
forming an nFET S/D region on physically exposed sidewalls of each Si channel material nanosheet of the second nanosheet stack and on the dielectric material.

8. The method of claim 7 , further comprising forming a dielectric isolation layer on a surface of the semiconductor substrate and beneath the vertical stack of first and second nanosheet stacks prior to forming the nFET S/D regions.

9. The method of claim 7 , further comprising forming a shared S/D contact structure on a first side of the suspended Si channel material nanosheets and the suspended SiGe channel material nanosheets, wherein the shared contact structure passes through one of the nFET S/D regions, the dielectric material and into one of the underlying pFET S/D regions.

10. The method of claim 1 , wherein the condensation anneal is performed at a temperature of from 350° C. to less than 800° C. and in an inert ambient.

11. The method of claim 1 , wherein the removing the germanium oxide layer from each suspended Si channel material nanosheet includes etching with deionized water.

12. The method of claim 1 , wherein the first germanium content is from 10 atomic percent germanium to 40 atomic percent germanium, the second germanium content is from 10 atomic percent to 25 atomic percent, and the third germanium content is from 20 atomic percent to 50 atomic percent.

13. The method of claim 1 , wherein the thinned SiGe material nanosheet is positioned between a first SiGe channel extension region and a second SiGe extension channel region.

14. The method of claim 13 , wherein collectively the thinned SiGe material nanosheet, the first SiGe channel extension region and a second SiGe extension channel region provide a dogbone shaped structure.

15. The method of claim 1 , wherein the work function metal is a single work function metal.

16. The method of claim 15 , wherein the single work function metal is a n-type work function metal or a p-type work function metal.

17. The method of claim 1 , wherein the suspended SiGe channel material nanosheets provide a channel region for a pFET containing device, and the Si channel material nanosheet provide a channel region for an nFET containing device.

18. The method of claim 1 , wherein the forming of the vertical stack of the first nanosheet stack and the vertical stack of the second nanosheet stack comprises:
forming a first semiconductor material stack of alternating layers of a sacrificial silicon germanium (SiGe) layer having the first germanium content and a precursor SiGe channel material layer having the second germanium content, and a second semiconductor material stack of alternating layers of a sacrificial SiGe layer having the first germanium content and a Si channel material layer, wherein the first semiconductor material stack is located on a topmost surface of the semiconductor substrate, and the second semiconductor material stack is located on a topmost surface of the first semiconductor material stack;
forming the sacrificial gate structure and the dielectric spacer on the first semiconductor material stack and the second semiconductor material stack; and
removing physically exposed portions of the first semiconductor material stack and the second semiconductor material stack.

19. The method of claim 18 , wherein the forming the first material stack and the forming of the second semiconductor material stack comprises an epitaxial growth process.

20. The method of claim 18 , wherein a bottommost sacrificial SiGe layer of the second semiconductor material stack has a thickness that is greater than a thickness of the other sacrificial SiGe layers.

Assignees

• IBM

Inventors

• Lee Choonghyun
• Zhang Jingyun
• Hashemi Pouya
• Ando Takashi
• Reznicek Alexander

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title