Monolithic conductive columns in a semiconductor device and associated methods

Patent metadata

Field	Value
Publication number	US-12183716-B2
Application number	US-202217711583-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Feb 11, 2022
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a base die, including:
a semiconductor substrate including an upper surface,
a die conductive pad and a mold conductive pad at the upper surface, wherein the mold conductive pad is laterally spaced from the die conductive pad, and
a base dielectric layer disposed over the die conductive pad, the mold conductive pad, and the upper surface;

a plurality of dies, each including:
a semiconductor substrate including an upper surface and a lower surface,
a conductive pad at the lower surface having a bottom surface opposite the lower surface,
a lower dielectric layer disposed over the conductive pad and the lower surface,
a die opening extending through the semiconductor substrate and the conductive pad from the bottom surface to the upper surface, and defining a die opening side wall of the semiconductor substrate and a side surface of the conductive pad,
a non-conductive liner coating the die opening side wall, and
an upper dielectric layer disposed over the upper surface, wherein the plurality of dies is stacked over the base die such that the die opening of each of the plurality of dies is vertically aligned with the die conductive pad;

a molding material laterally adjacent to the plurality of dies;
a die monolithic conductive column extending from the die conductive pad through the die opening of each of the plurality of dies and in direct contact with the side surface of the conductive pad of each of the plurality of dies; and
a mold monolithic conductive column extending from the mold conductive pad through the molding material.

2. The semiconductor device assembly of claim 1 , wherein the upper dielectric layer of at least one of the plurality of dies comprises the same material as and is integrally formed with the non-conductive liner of the at least one of the plurality of dies.

3. The semiconductor device assembly of claim 1 , wherein the die conductive pad and the mold conductive pad each have an upper surface in the same first plane and the semiconductor device assembly has a second plane above the first plane, wherein the die monolithic conductive column and the mold monolithic column extend from the die conductive pad upper surface and the mold conductive pad upper surface, respectively, to the second plane.

4. The semiconductor device assembly of claim 1 , wherein the semiconductor substrate of the base die further includes a lower surface opposite the upper surface and the semiconductor device assembly further comprises:
a die external connector assembly, including:
a die external conductive structure extending through the base die semiconductor substrate from the upper surface at the die conductive pad to the lower surface, and
a die electric connector coupled to the lower surface of the base die semiconductor substrate at the die external conductive structure; and

a mold external connector assembly, including:
a mold external conductive structure extending through the base die from the upper surface at the mold conductive pad to the lower surface, and
a mold electric connector coupled to the lower surface of the base die at the mold external conductive structure.

5. The semiconductor device assembly of claim 4 , wherein the semiconductor device assembly is configured such that the die electric connector is in electrical communication with each of the plurality of dies via the die external conductive structure, the die conductive pad, the die monolithic conductive column, and the conductive pad of each of the plurality of dies.

6. The semiconductor device assembly of claim 1 , wherein the semiconductor device assembly further comprises:
a die electric connector coupled to an exterior upper surface of the semiconductor device assembly and in electric communication with the die monolithic conductive column; and
a mold electric connector coupled to the exterior upper surface and in electric communication with the mold monolithic conductive column.

7. The semiconductor device assembly of claim 6 , wherein the semiconductor device assembly comprises:
an uppermost die of the plurality of dies as a top die stacked over the base die; and
an assembly cover layer disposed over the dielectric layer of the uppermost die and the molding material, the assembly cover layer including an upper surface defining the exterior upper surface of the semiconductor device assembly.

8. The semiconductor device assembly of claim 1 , wherein one of the plurality of dies further includes a thermal pad on the upper or lower surface thereof and configured to increase a thermal transmissivity of the one of the plurality of dies.

9. The semiconductor device assembly of claim 1 , wherein the base die further includes a thermal pad on the upper surface thereof and configured to increase a thermal transmissivity of the base die.

10. A semiconductor device, comprising:
a semiconductor die, including:
a semiconductor substrate having a first surface and a second surface opposite the first surface,
a conductive pad at the first surface of the semiconductor substrate,
a first dielectric layer disposed over the first surface and the conductive pad,
an opening extending through the semiconductor substrate from the conductive pad at the first surface to the second surface, and defining an opening side wall,
a non-conductive liner coating at least the opening side wall,
a plug of non-conductive material filling the opening, and
a second dielectric layer covering the second surface and the plug; and

a molding material laterally adjacent to the semiconductor die.

11. The semiconductor device of claim 10 , further comprising:
a second semiconductor die, including:
a second semiconductor substrate with a top surface and a bottom surface opposite the top surface,
a second conductive pad at the bottom surface of the second semiconductor substrate,
a bottom dielectric layer disposed over the bottom surface and the second conductive pad, and
a second opening extending through the second semiconductor substrate from the second conductive pad to the top surface, wherein the bottom dielectric layer is bonded to the second dielectric layer with the second opening in alignment with the opening, and wherein the molding material is further laterally adjacent to the second semiconductor die.

12. The semiconductor device of claim 10 , wherein a second conductive pad is at the first surface of the semiconductor substrate and a second opening extends through the semiconductor substrate from the second conductive pad to the second surface of the semiconductor substrate.

13. The semiconductor device of claim 12 , wherein the second opening defines a second opening side wall with a second non-conductive liner coating at least the second opening side wall and a second plug of non-conductive material filling the second opening.

14. The semiconductor device of claim 10 , wherein the non-conductive liner and the plug comprising the same non-conductive material and integrally formed together.

15. The semiconductor device of claim 10 , wherein the semiconductor die further includes a thermal pad at the first surface and adjacent to the conductive pad.

16. The semiconductor device of claim 10 , wherein the non-conductive liner, the plug, and the second dielectric layer comprising the same non-conductive material.

17. The semiconductor device of claim 16 , wherein the non-conductive liner, the plug, and the second dielectric layer are integrally formed together.

18. A method of manufacturing a semiconduct

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Kirby Kyle K
• Street Bret K
• Parekh Kunal R

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title