Semiconductor package

Patent metadata

Field	Value
Publication number	US-12183665-B2
Application number	US-202418423229-A
Country	US
Kind code	B2
Filing date	Jan 25, 2024
Priority date	May 3, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, comprising:
providing a carrier substrate having a connection hole on a first carrier substrate;
providing first and second semiconductor chips in the connection hole on the first carrier substrate;
forming a molding layer covering the carrier substrate and upper surfaces of the first and second semiconductor chips;
attaching a second carrier substrate on the molding layer;
removing the first carrier substrate;
turning the second carrier substrate to allow lower surfaces of the first and second semiconductor chips to face upwards;
forming a first redistribution substrate on the lower surfaces of the first and second semiconductor chips;
mounting a connection semiconductor chip and a capacitor chip on the first redistribution substrate, the capacitor chip horizontally spaced apart from the connection semiconductor chip;
forming an interposer molding layer covering upper surfaces of the connection semiconductor chip; and
forming a second redistribution substrate on the interposer molding layer.

2. The method of manufacturing the semiconductor package of claim 1 , further comprising forming conductive posts on the first redistribution substrate before forming the interposer molding layer,
wherein the conductive posts connect the first redistribution substrate and the second redistribution substrate.

3. The method of manufacturing the semiconductor package of claim 2 , further comprising grinding the interposer molding layer to expose surfaces of the conductive posts before forming the second redistribution substrate.

4. The method of manufacturing the semiconductor package of claim 3 , wherein an upper surface of the connection semiconductor chip is not exposed during grinding the interposer molding layer.

5. The method of manufacturing the semiconductor package of claim 1 , after forming the second redistribution substrate, further comprising:
turning the second carrier substrate upside down again to locate the lower surfaces of the first and second semiconductor chips facing downward;
removing the second carrier substrate; and
grinding the molding layer to expose upper surfaces of the first and second semiconductor chips.

6. The method of manufacturing the semiconductor package of claim 5 , wherein the molding layer covers an upper surface and a sidewall of the carrier substrate, and sidewalls of the first and second semiconductor chips.

7. The method of manufacturing the semiconductor package of claim 5 , further comprising disposing a thermal dissipation plate contacting at least one of the upper surfaces of the first and semiconductor chips after grinding the molding layer.

8. The method of manufacturing the semiconductor package of claim 1 , wherein an upper surface of the first semiconductor chip is at a lever higher than a level of an upper surface of the carrier substrate.

9. The method of manufacturing the semiconductor package of claim 1 , wherein mounting the capacitor chip horizontally spaced apart from the connection semiconductor chip on the first redistribution before forming the interposer molding layer.

10. The method of manufacturing the semiconductor package of claim 1 , wherein the first redistribution substrate includes a first redistribution dielectric layer and first redistribution patterns in the first redistribution dielectric layer, and
wherein each of the first redistribution patterns includes a first wire part and a first via part on the first wire part.

11. The method of manufacturing the semiconductor package of claim 10 , wherein the second redistribution substrate includes a second redistribution dielectric layer and second redistribution patterns in the second redistribution dielectric layer,
wherein each of the second redistribution patterns includes a second wire part and a second via part on the second wire part.

12. The method of manufacturing the semiconductor package of claim 1 , wherein an upper surface and a lower surface of the connection semiconductor chip are covered by the interposer molding layer.

13. The method of manufacturing the semiconductor package of claim 1 , wherein
a first portion of the connection semiconductor chip vertically overlaps a portion of the first semiconductor chip, and
a second portion of the connection semiconductor chip vertically overlaps a portion of the second semiconductor chip.

14. A method of manufacturing a semiconductor package, comprising:
providing a carrier substrate having a connection hole on a first carrier substrate;
providing first and second semiconductor chips in the connection hole on the first carrier substrate;
forming a preliminary molding layer covering the carrier substrate and upper surfaces of the first and second semiconductor chips;
attaching a second carrier substrate on the preliminary molding layer;
removing the first carrier substrate;
turning the second carrier substrate to allow lower surfaces of the first and second semiconductor chips to face upwards;
forming a first redistribution substrate including a first redistribution dielectric layer and first redistribution patterns in the first redistribution dielectric layer, on the lower surfaces of the first and second semiconductor chips;
forming conductive patterns connected to the first redistribution patterns on the first redistribution substrate;
forming conductive posts on the conductive patterns on an edge region of the first redistribution substrate;
mounting a connection semiconductor chip connected to the conductive patterns and a capacitor chip horizontally spaced apart from the connection semiconductor chip on a center region of the first redistribution substrate;
forming an interposer molding layer covering upper surfaces of the connection semiconductor chip;
forming a second redistribution substrate including a second redistribution dielectric layer and second redistribution patterns in the second redistribution dielectric layer, on the interposer molding layer,
turning the second carrier substrate again to allow the lower surfaces of the first and second semiconductor chips to face downwards;
removing the second carrier substrate; and
forming a molding layer by grinding the preliminary molding layer to expose upper surfaces of the first and second semiconductor chips.

15. The method of manufacturing the semiconductor package of claim 14 , further comprising disposing a thermal dissipation plate contacting at least one of the upper surfaces of the first and semiconductor chips after forming a molding layer.

16. The method of manufacturing the semiconductor package of claim 14 , an upper surface and lower surface of the connection semiconductor chip are covered by the interposer molding layer.

17. The method of manufacturing the semiconductor package of claim 14 , the molding layer covers an upper surface of the carrier substrate, and
the molding layer exposes a top surface of the first semiconductor chip and a top surface of the second semiconductor chip.

18. The method of manufacturing the semiconductor package of claim 14 , wherein the carrier substrate includes a conductive structure and a base layer,
wherein the conductive structure is connected to the first redistribution substrate.

19. The method of manufacturing the semiconductor package of claim 18 , wherein the conductive structure is connected to the conductive posts on the edge region of the first redistribution substrate.

20. The method of manufacturing the semiconductor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Kim Jeongseok
• Mun Kyung Don

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title