Reliable microstrip routing for electronics components

Patent metadata

Field	Value
Publication number	US-9607947-B2
Application number	US-201615183645-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jun 28, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

First claim

What is claimed is:

1. A semiconductor package, comprising:
first and second adjacent semiconductor dies;
a silicon interposer structure disposed below and electrically coupling the first and second semiconductor dies;
an organic package substrate disposed below and electrically coupled to the silicon interposer structure by a plurality of conductive contacts, the organic package substrate comprising a plurality of routing layers therein;
a plurality of discrete metal planes disposed at an uppermost metallization layer of the plurality of routing layers of the organic package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the silicon interposer structure; and
microstrip routing disposed at the uppermost metallization layer of the plurality of routing layers of the organic package substrate, from the plan view perspective, outside of the perimeter of the silicon interposer structure.

2. The semiconductor package of claim 1 , further comprising:
an epoxy fillet layer disposed between the silicon interposer structure and the organic package substrate and surrounding the plurality of conductive contacts.

3. The semiconductor package of claim 2 , wherein the plurality of discrete metal planes is for arresting propagation of one or more cracks from the epoxy fillet layer or a solder resist SR layer under the epoxy fillet or a die corner.

4. The semiconductor package of claim 2 , further comprising:
a crack in the epoxy fillet layer or a solder resist SR layer under the epoxy fillet or a die corner, wherein propagation of the crack is arrested at one of the plurality of discrete metal planes.

5. The semiconductor package of claim 2 , further comprising:
a solder resist disposed on the uppermost metallization layer and surrounding the plurality of conductive contacts, wherein the epoxy fillet layer is disposed on the solder resist.

6. The semiconductor package of claim 5 , further comprising:
a trench formed in the solder resist, from the plan view perspective, outside of the perimeter of the silicon interposer structure, the trench providing a keep out zone for the epoxy fillet layer.

7. The semiconductor package of claim 6 , wherein the trench is formed only partially into the solder resist, and wherein, from the plan view perspective, a portion of the microstrip routing is underneath the trench.

8. The semiconductor package of claim 7 , wherein the solder resist comprises a first solder resist layer disposed on a second solder resist layer, and wherein the trench is disposed in the first solder resist layer but not in the second solder resist layer.

9. The semiconductor package of claim 1 , wherein the organic package substrate is electrically coupled to the silicon interposer structure by one or more through-silicon-vias (TSVs) disposed in the silicon interposer structure.

Assignees

• Karhade Omkar G
• Altunyurt Nevin
• Lee Kyu Oh
• Bharath Krishna
• Intel Corp

Inventors

• Karhade Omkar G
• Altunyurt Nevin
• Lee Kyu Oh
• Bharath Krishna

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title