Enhancing tunnel magnetoresistance in memory device comprising a memory cell with a memory element coupled between a switch and a negative resistance device

Patent metadata

Field	Value
Publication number	US-12183379-B2
Application number	US-202217994407-A
Country	US
Kind code	B2
Filing date	Nov 28, 2022
Priority date	Jul 31, 2019
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

First claim

What is claimed is:

1. A memory device, comprising:
at least one memory cell,
wherein at least one memory cell comprising:
a switch, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line;
a memory element; and
a negative resistance device,

wherein the memory element is coupled between a second terminal of the switch and a first terminal of the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line,
wherein during a read operation in the memory device, a read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state.

2. The memory device of claim 1 , wherein a loading of the at least one memory cell is reduced while the negative resistance device is entering into the negative resistance state.

3. The memory device of claim 1 , wherein the negative resistance device is an ovonic threshold switch (OTS), and the switch is a CMOS transistor.

4. The memory device of claim 1 , wherein the memory element is a magnetic tunnel junction (MTJ) device.

5. The memory device of claim 1 , wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line.

6. The memory device of claim 1 , wherein the predetermined threshold voltage of the negative resistance device is adjusted with different materials.

7. The memory device of claim 6 , wherein the negative resistance device is a metal-semiconductor-metal (MSM).

8. The memory device of claim 6 , wherein the negative resistance device is a mixed-ionic-electronic-conduction device (MIEC).

9. The memory device of claim 6 , wherein the negative resistance device comprises at least one of the elements in a Chalcogenide group.

10. The memory device of claim 1 , wherein during a write operation in the memory device, a write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state.

11. A memory device, comprising:
a driver configured to generate a read voltage and a write voltage to perform a read operation and a write operation in the memory device;
a sense amplifier;
a data output, configured to receive an input from the sense amplifier and generate an output;
a memory cell array, wherein the memory cell array comprising:
at least one memory cell,
wherein the at least one memory cell comprising:
a switch, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line;
a memory element; and
a negative resistance device,

wherein the memory element is coupled between a second terminal of the switch and a first terminal of the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line,
wherein during the read operation in the memory device, the read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state.

12. The memory device of claim 11 , wherein a loading of the at least one memory cell is reduced while the negative resistance device is entering into the negative resistance state.

13. The memory device of claim 11 , wherein the negative resistance device is an ovonic threshold switch (OTS), the switch is a CMOS transistor, and the memory element is a magnetic tunnel junction (MTJ) device.

14. The memory device of claim 11 , wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line.

15. The memory device of claim 11 , wherein during the write operation in the memory device, the write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state.

16. A method to control a memory cell in a memory device, comprising:
determine whether the memory cell is in a read operation or not, wherein the memory cell includes a switch, a memory element, and a negative resistance device, a first terminal of the switch is coupled to a common source line and a control terminal of the switch is coupled to a word line, the memory element is coupled between the switch and the negative resistance device, and a second terminal of the negative resistance device is coupled to a bit line; and
during the read operation of the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device to the negative resistance device for making the negative resistance device enter into a negative resistance state.

17. The method of claim 16 , wherein the read voltage is applied to the negative resistance device by a voltage difference between the bit line and the common source line.

18. The method of claim 16 , further comprising:
determine whether the memory cell is in a write operation or not;
wherein during the write operation, apply a write voltage greater than the predetermined threshold voltage to the negative resistance device for making the negative resistance device enter into a low resistance state.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wen-Chin
• Yu Hung-Chang

Classifications

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title