Method for enhancing tunnel magnetoresistance in memory device

Patent metadata

Field	Value
Publication number	US-10998024-B2
Application number	US-202016805839-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Jul 31, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

First claim

What is claimed is:

1. A memory cell array, comprising:
a plurality of memory cells,
a plurality of word lines;
a plurality of bit lines; and
a plurality of common source lines,
wherein each of the memory cells comprising:
a switch, a first terminal of the switch is coupled to one of the common source lines and a control terminal of the switch is coupled to one of the word lines;
a memory element, a first terminal of the memory element is coupled to a second terminal of the switch; and
a negative resistance device, a first terminal of the negative resistance device is coupled to a second terminal of the memory element, and a second terminal of the negative resistance device is coupled to one of the bit lines,
wherein the switch, the memory element, and the negative resistance device are coupled in series,
wherein during a read operation in the memory cell array, a read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state.

2. The memory cell array of claim 1 , wherein the negative resistance device is an ovonic threshold switch (OTS).

3. The memory cell array of claim 1 , wherein the switch is a CMOS transistor.

4. The memory cell array of claim 1 , wherein the memory element is a magnetic tunnel junction (MTJ) device.

5. The memory cell array of claim 1 , wherein the read voltage of is applied to the negative resistance device by a voltage difference between the one of the bit lines and one of the common source lines.

6. The memory cell array of claim 1 , wherein a loading of each of the memory cells are reduced while the negative resistance device entering into the negative resistance state.

7. The memory cell array of claim 1 , wherein the predetermined threshold voltage of the negative resistance device is adjusted with different materials.

8. The memory cell array of claim 7 , wherein the negative resistance device is a metal-semiconductor-metal (MSM).

9. The memory cell array of claim 7 , wherein the negative resistance device is a mixed-ionic-electronic-conduction device (MIEC).

10. The memory cell array of claim 7 , wherein the negative resistance device comprises at least one of the elements in a Chalcogenide group.

11. The memory cell array of claim 1 , wherein during a write operation in the memory cell array, a write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state.

12. A memory device, comprising:
a driver configured to generate a read voltage and a write voltage to perform a read operation and a write operation in the memory device;
a sense amplifier;
a data output, configured to receive an input from the sense amplifier and generates an output;
a memory cell array, wherein the memory cell array comprising:
a plurality of memory cells,
a plurality of word lines;
a plurality of bit lines; and
a plurality of common source lines,
wherein each of the memory cells comprising:
a switch, a first terminal of the switch is coupled to one of the common source lines and a control terminal of the switch is coupled to one of the word lines;
a memory element, a first terminal of the memory element is coupled to a second terminal of the switch; and
a negative resistance device, a first terminal of the negative resistance device is coupled to a second terminal of the memory element, and a second terminal of the negative resistance device is coupled to one of the bit lines,
wherein the switch, the memory element, and the negative resistance device are coupled in series,
a wherein during the read operation of the memory cells, the read voltage greater than a predetermined threshold voltage of the negative resistance device is applied to the negative resistance device for making the negative resistance device enter into a negative resistance state.

13. The memory device of claim 12 , wherein the negative resistance device is an ovonic threshold switch (OTS).

14. The memory device of claim 12 , wherein the memory element is a magnetic tunnel junction (MTJ) device.

15. The memory device of claim 12 , wherein the read voltage of is applied to the negative resistance device by a voltage difference between the one of the bit lines and one of the common source lines.

16. The memory device of claim 12 , wherein a loading of each of the memory cells are reduced while the negative resistance device is entering into the negative resistance state.

17. The memory device of claim 12 , wherein during a write operation in the memory device, the write voltage greater than the predetermined threshold voltage is applied to the negative resistance device for making the negative resistance device enter into a low resistance state.

18. A method to control a memory cell in a memory device, wherein the memory cell includes a switch, a memory element and a negative resistance device coupled in series, wherein the switch includes a control terminal coupled to a control line, comprising:
determine whether the memory cell is in a read operation or not;
a during the read operation of the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device to the negative resistance device for making the negative resistance device enter into a negative resistance state.

19. The method of claim 18 , wherein the read voltage of is applied to the negative resistance device by a voltage difference between a bit line and a common source line.

20. The method of claim 18 , further comprising:
determine whether the memory cell is in a write operation or not;
wherein during the write operation, apply the write voltage greater than the predetermined threshold voltage for making the negative resistance device enter into a low resistance state.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wen-Chin
• Yu Hung-Chang

Classifications

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title