Embedded metal lines

Patent metadata

Field	Value
Publication number	US-12170268-B2
Application number	US-202418614310-A
Country	US
Kind code	B2
Filing date	Mar 22, 2024
Priority date	Mar 29, 2019
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.

First claim

What is claimed is:

1. A method comprising:
providing a substrate having a back side and a top side opposite the back side, the substrate comprising active devices coupled to buried lines extending parallel to a major surface of the substrate, the active devices closer to the top side than the back side of the substrate; and
exposing the buried lines from the back side of the substrate.

2. The method of claim 1 , wherein exposing the buried lines from the back side of the substrate comprises polishing from the back side of the substrate.

3. The method of claim 2 , wherein the substrate is attached to a handle substrate prior to polishing.

4. The method of claim 1 , further comprising modifying or replacing at least a portion of the buried lines to form buried conductive lines (BCLs) that have a conductivity higher than the buried lines.

5. The method of claim 4 , further comprising configuring the BCLs and active devices to operate as a memory array.

6. The method of claim 4 , wherein the buried lines comprise silicon, and wherein modifying or replacing comprises reacting the silicon with a metal to form a silicide region.

7. The method of claim 4 , wherein the buried lines comprise silicon, and wherein modifying or replacing comprises removing a portion of the silicon and replacing it with a conductive material.

8. The method of claim 7 , wherein the conductive material comprises a barrier layer contacting the silicon and a metal or metal alloy contacting the barrier layer.

9. The method of claim 7 , wherein the conductive material comprises a silicide contacting the silicon and a metal or metal alloy contacting the silicide.

10. The method of claim 4 , wherein the buried lines comprise silicon, and wherein the silicon is replaced with a metal-containing conductive material.

11. The method of claim 4 , wherein the buried lines comprise silicon, and wherein modifying or replacing comprises epitaxially growing in-situ doped silicon.

12. The method of claim 4 , wherein forming the BCLs comprises forming a first buried conductive line (BCL) that is substantially parallel to a second BCL, and wherein the first BCL is isolated from the second BCL by an isolation region.

13. The method of claim 12 , further comprising replacing a portion of the isolation region with a low-k dielectric region.

14. The method of claim 4 , wherein modifying or replacing further comprises:
etching a portion of each of the buried lines; and
using a damascene process to add a conductive material in regions where the buried lines were etched.

15. The method of claim 14 , wherein the conductive material comprises copper, tungsten, or aluminum.

16. The method of claim 1 , wherein the substrate is a first substrate and the method further comprises coupling, electronically and mechanically, a second substrate to the first substrate to form a three-dimensional structure.

17. The method of claim 16 , further comprising coupling, electronically and mechanically, a third substrate to the second substrate.

18. The method of claim 16 , wherein coupling comprises direct bonding.

19. The method of claim 1 , wherein the substrate is attached to a handle substrate prior to exposing the buried lines.

20. The method of claim 1 , further comprising:
creating isolation regions, wherein a first buried line and a second buried line are formed adjacent opposite sides of an individual one of the isolation regions.

21. The method of claim 20 , wherein at least a portion of the isolation regions are replaced with a low-k dielectric.

22. The method of claim 1 , wherein at least some of the active devices are aligned with at least some of the buried lines.

23. The method of claim 1 , wherein the active devices comprise transistors having a source/drain region vertically in line with the buried lines.

24. A method comprising:
providing a substrate having a back side and a front side opposite the back side;
forming buried lines in the substrate, the buried lines extending parallel to a major surface of the substrate;
forming active devices in and over the front side of the substrate; and
exposing the buried lines from the back side of the substrate.

25. The method of claim 24 , further comprising, after exposing replacing or modifying at least a portion of the buried lines from the back side to form a higher conductivity material.

26. The method of claim 25 , wherein the higher conductivity material comprises metal.

27. The method of claim 24 , wherein forming the active devices comprises forming transistors, at least some of the transistors electrically connected to the buried lines at the front side of the substrate.

28. The method of claim 27 , wherein the at least some of the transistors are vertically in line with the corresponding buried lines.

Assignees

• Adeia Semiconductor Tech Llc

Inventors

• Morein Stephen

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title